KEYMGR_DPE Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: 1ac1583

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	231.590s	76251.088us	50	50	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.170s	31.789us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.100s	92.142us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	10.710s	593.775us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	6.570s	4193.272us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.740s	65.418us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.100s	92.142us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.570s	4193.272us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	intr_test	keymgr_dpe_intr_test	0.820s	15.811us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.510s	26.917us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	3.830s	179.371us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	3.830s	179.371us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.170s	31.789us	5	5	100.00
		keymgr_dpe_csr_rw	1.100s	92.142us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.570s	4193.272us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.490s	286.147us	19	20	95.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.170s	31.789us	5	5	100.00
		keymgr_dpe_csr_rw	1.100s	92.142us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.570s	4193.272us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.490s	286.147us	19	20	95.00
V2		TOTAL			139	140	99.29
V2S	tl_intg_err	keymgr_dpe_tl_intg_err	5.550s	886.546us	20	20	100.00
		keymgr_dpe_sec_cm	13.860s	2286.487us	5	5	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.200s	172.207us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.200s	172.207us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.200s	172.207us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.200s	172.207us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	6.050s	266.124us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	13.860s	2286.487us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	13.860s	2286.487us	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			309	310	99.68

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.62	97.62	90.39	63.15	75.68	94.61	97.64	17.25

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:642) [keymgr_dpe_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
  • Test keymgr_dpe_same_csr_outstanding has 1 failures.

    • 10.keymgr_dpe_same_csr_outstanding.79513472775180545595720052353888113293242334772323920457598653800556265055094
      Line 77, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/10.keymgr_dpe_same_csr_outstanding/latest/run.log

        UVM_ERROR @   2129100 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.keymgr_dpe_common_vseq] Check failed masked_data == exp_data (256 [0x100] vs 0 [0x0]) addr 0xf8cd8dd0 read out mismatch
        UVM_INFO @   2129100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---