1ac1583| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 86.770s | 16767.009us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.540s | 32.998us | 10 | 10 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.570s | 40.783us | 40 | 40 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 18.200s | 2892.148us | 10 | 10 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 8.290s | 1206.256us | 10 | 10 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 3.180s | 89.986us | 40 | 40 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.570s | 40.783us | 40 | 40 | 100.00 |
| kmac_csr_aliasing | 8.290s | 1206.256us | 10 | 10 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 1.090s | 13.368us | 10 | 10 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.870s | 200.785us | 10 | 10 | 100.00 |
| V1 | TOTAL | 230 | 230 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 3644.660s | 141391.264us | 100 | 100 | 100.00 |
| V2 | burst_write | kmac_burst_write | 1236.900s | 31414.325us | 99 | 100 | 99.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 1739.020s | 62031.589us | 10 | 10 | 100.00 |
| kmac_test_vectors_sha3_256 | 1652.490s | 122083.376us | 10 | 10 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 1722.350s | 187090.183us | 10 | 10 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 1222.890s | 182828.398us | 10 | 10 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1864.620s | 137564.880us | 10 | 10 | 100.00 | ||
| kmac_test_vectors_shake_256 | 2024.600s | 91665.884us | 10 | 10 | 100.00 | ||
| kmac_test_vectors_kmac | 3.550s | 313.475us | 10 | 10 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 3.630s | 355.231us | 10 | 10 | 100.00 | ||
| V2 | sideload | kmac_sideload | 500.890s | 22764.707us | 100 | 100 | 100.00 |
| V2 | app | kmac_app | 376.160s | 347202.350us | 100 | 100 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 326.780s | 15729.430us | 20 | 20 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 391.670s | 27909.425us | 100 | 100 | 100.00 |
| V2 | error | kmac_error | 458.170s | 82714.642us | 99 | 100 | 99.00 |
| V2 | key_error | kmac_key_error | 21.590s | 30463.880us | 99 | 100 | 99.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 103.030s | 10048.829us | 88 | 100 | 88.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 49.700s | 25704.567us | 40 | 40 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 50.870s | 2259.428us | 40 | 40 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 94.660s | 16975.027us | 20 | 20 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 52.410s | 3552.856us | 100 | 100 | 100.00 |
| V2 | stress_all | kmac_stress_all | 3622.230s | 197527.934us | 98 | 100 | 98.00 |
| V2 | intr_test | kmac_intr_test | 1.200s | 203.975us | 100 | 100 | 100.00 |
| V2 | alert_test | kmac_alert_test | 1.440s | 419.614us | 100 | 100 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 4.780s | 197.569us | 40 | 40 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 4.780s | 197.569us | 40 | 40 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.540s | 32.998us | 10 | 10 | 100.00 |
| kmac_csr_rw | 1.570s | 40.783us | 40 | 40 | 100.00 | ||
| kmac_csr_aliasing | 8.290s | 1206.256us | 10 | 10 | 100.00 | ||
| kmac_same_csr_outstanding | 3.370s | 423.671us | 40 | 40 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.540s | 32.998us | 10 | 10 | 100.00 |
| kmac_csr_rw | 1.570s | 40.783us | 40 | 40 | 100.00 | ||
| kmac_csr_aliasing | 8.290s | 1206.256us | 10 | 10 | 100.00 | ||
| kmac_same_csr_outstanding | 3.370s | 423.671us | 40 | 40 | 100.00 | ||
| V2 | TOTAL | 1463 | 1480 | 98.85 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.860s | 355.062us | 40 | 40 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.860s | 355.062us | 40 | 40 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.860s | 355.062us | 40 | 40 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.860s | 355.062us | 40 | 40 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 7.140s | 449.338us | 38 | 40 | 95.00 |
| V2S | tl_intg_err | kmac_sec_cm | 62.440s | 3402.515us | 10 | 10 | 100.00 |
| kmac_tl_intg_err | 5.460s | 1318.228us | 40 | 40 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.460s | 1318.228us | 40 | 40 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 52.410s | 3552.856us | 100 | 100 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 86.770s | 16767.009us | 100 | 100 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 500.890s | 22764.707us | 100 | 100 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.860s | 355.062us | 40 | 40 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 62.440s | 3402.515us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 62.440s | 3402.515us | 10 | 10 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 62.440s | 3402.515us | 10 | 10 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 86.770s | 16767.009us | 100 | 100 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 52.410s | 3552.856us | 100 | 100 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 62.440s | 3402.515us | 10 | 10 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 424.850s | 13686.889us | 20 | 20 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 86.770s | 16767.009us | 100 | 100 | 100.00 |
| V2S | TOTAL | 148 | 150 | 98.67 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 260.050s | 14773.173us | 16 | 20 | 80.00 |
| V3 | TOTAL | 16 | 20 | 80.00 | |||
| TOTAL | 1857 | 1880 | 98.78 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.35 | 99.27 | 94.49 | 99.89 | 80.99 | 97.15 | 97.83 | 97.86 |
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
0.kmac_stress_all_with_rand_reset.69084951503169467524898701451321258675924880703072306052884609917008253668854
Line 332, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24417796043 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 24417796043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_stress_all_with_rand_reset.104290048665026148552137733570828953914302403498066994920021495147649894932553
Line 202, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16117118710 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16117118710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
18.kmac_stress_all.67707879830514765388745516497010189836761585258353721344247904589743969347092
Line 359, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_stress_all/latest/run.log
UVM_ERROR @ 34913366317 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 34913366317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.kmac_stress_all.31924633044861844968646121684399186746661310059315255871891349371318669767199
Line 131, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/36.kmac_stress_all/latest/run.log
UVM_ERROR @ 3749952517 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 3749952517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 2 failures:
17.kmac_shadow_reg_errors_with_csr_rw.88019835239778484963922600692550518652152224788981393829813078546058548319536
Line 312, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 42407344 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1207195226 [0x47f4565a] vs 2405222386 [0x8f5cc7f2]) Regname: kmac_reg_block.prefix_2.prefix_0 reset value: 0x0
UVM_INFO @ 42407344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.kmac_shadow_reg_errors_with_csr_rw.11404764885234808644541424399010896760957633884000432504267095361181015306216
Line 269, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 125516005 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1490791231 [0x58dbab3f] vs 2044324246 [0x79d9e996]) Regname: kmac_reg_block.prefix_0.prefix_0 reset value: 0x0
UVM_INFO @ 125516005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 2 failures:
5.kmac_sideload_invalid.106526609463037697274767008239915802366574863230640198344748055444636254591845
Line 91, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10303660430 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcc1cb000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10303660430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.kmac_sideload_invalid.60560074095810805816461340524359884132638838793404223984503825326383945359859
Line 91, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/22.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10504795477 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdf211000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10504795477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 2 failures:
9.kmac_sideload_invalid.113762976881606728264525746526221901285044952909891592330659918192819007229248
Line 97, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/9.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10208160946 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcfa96000, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 10208160946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.kmac_sideload_invalid.56234173508364256355060165243276646078060415592143931808281090342567543621033
Line 99, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10351123647 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5add6000, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 10351123647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:
10.kmac_sideload_invalid.43507860989941456881270462360120327519108758425800466003113202673234384265932
Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10076075461 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x52ba4000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10076075461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.kmac_sideload_invalid.35764748101148383699997670704204586813728590842949812006838368964426237208718
Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10129002662 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x46397000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10129002662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test kmac_burst_write has 1 failures.
22.kmac_burst_write.99925362180956492527306213966720549269137124687454537196081643389267023468836
Line 231, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/22.kmac_burst_write/latest/run.log
UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_error has 1 failures.
48.kmac_error.106604574877559476790158797155323385359057992612107475337104859339178013646377
Line 169, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/48.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
9.kmac_stress_all_with_rand_reset.58226857661525761471888467563540903564454782017829560375237563560624698590320
Line 344, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21202987984 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 21202987984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
8.kmac_sideload_invalid.104933644071428192616516579170497384810643604947285481273162688167356201878485
Line 84, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10842380838 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x749b2000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10842380838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
11.kmac_sideload_invalid.62666444588003327317975171884452785960701279190823884124579680957279267028260
Line 82, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10048829472 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3b9ca000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10048829472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
14.kmac_sideload_invalid.62465472278430413533432662489337005540635454852817468247337291002193103758083
Line 90, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/14.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10175139554 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1a9ff000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10175139554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:
22.kmac_key_error.56888621553666942701799630463820194907267367066096648781331481714088454006379
Line 74, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/22.kmac_key_error/latest/run.log
UVM_ERROR @ 1172737212 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
UVM_INFO @ 1172737212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
23.kmac_sideload_invalid.57904911372936298127667634807396294409559937364205176710228978782060545936159
Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10082132800 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7bcb5000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10082132800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
40.kmac_sideload_invalid.89445883604520290884634421659031237414371293495674409326296011617023846246842
Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/40.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10082304344 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x281d8000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10082304344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
47.kmac_sideload_invalid.69109987246557097773245647722998858365532131815561747868112881050825635009113
Line 96, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/47.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10345521360 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x10b4f000, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10345521360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---