MBX Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: 1ac1583

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	69.000s	7666.327us	2	2	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	2.000s	17.799us	5	5	100.00
V1	csr_rw	mbx_csr_rw	2.000s	52.220us	20	20	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	6.000s	929.421us	5	5	100.00
V1	csr_aliasing	mbx_csr_aliasing	3.000s	223.354us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	3.000s	96.808us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	2.000s	52.220us	20	20	100.00
		mbx_csr_aliasing	3.000s	223.354us	5	5	100.00
V1		TOTAL			57	57	100.00
V2	mbx_stress	mbx_stress	72.000s	11335.967us	1	2	50.00
V2	mbx_max_activity	mbx_stress_zero_delays	29.000s	5680.494us	1	2	50.00
V2	mbx_imbx_oob	mbx_imbx_oob	25.000s	2036.195us	1	2	50.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	20.000s	1064.467us	5	5	100.00
V2	alert_test	mbx_alert_test	2.000s	59.054us	50	50	100.00
V2	intr_test	mbx_intr_test	2.000s	15.012us	50	50	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	6.000s	415.716us	20	20	100.00
V2	tl_d_illegal_access	mbx_tl_errors	6.000s	415.716us	20	20	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	2.000s	17.799us	5	5	100.00
		mbx_csr_rw	2.000s	52.220us	20	20	100.00
		mbx_csr_aliasing	3.000s	223.354us	5	5	100.00
		mbx_same_csr_outstanding	3.000s	116.033us	20	20	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	2.000s	17.799us	5	5	100.00
		mbx_csr_rw	2.000s	52.220us	20	20	100.00
		mbx_csr_aliasing	3.000s	223.354us	5	5	100.00
		mbx_same_csr_outstanding	3.000s	116.033us	20	20	100.00
V2		TOTAL			148	151	98.01
V2S	tl_intg_err	mbx_sec_cm	2.000s	20.515us	5	5	100.00
		mbx_tl_intg_err	3.000s	682.548us	20	20	100.00
V2S		TOTAL			25	25	100.00
		TOTAL			230	233	98.71

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
93.70	96.75	92.07	96.71	91.52	86.12	--	97.01	86.13

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 2 failures:

  • Test mbx_imbx_oob has 1 failures.

    • 0.mbx_imbx_oob.40433176028886403819182410323140886485940911257608561456654754139998135522597
      Line 88, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log

        UVM_ERROR @  55724866 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @  55724866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_stress_zero_delays has 1 failures.

    • 1.mbx_stress_zero_delays.39159740454134390254362798800788339642128917057274582074749396770092513524010
      Line 86, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @  40694750 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @  40694750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched has 1 failures:

  • Test mbx_stress has 1 failures.

    • 0.mbx_stress.96202191318852392757460032712065161433118562951989524990049081799364098152399
      Line 120, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log

        UVM_ERROR @ 108885752 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 322036202 [0x1331e1ea]) RDATA read data mismatched
        UVM_INFO @ 108885752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---