1ac1583| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 12.000s | 40.237us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 391.000s | 1291.917us | 100 | 100 | 100.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 6.000s | 23.705us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 5.000s | 14.694us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 6.000s | 66.060us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 4.000s | 25.376us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 11.000s | 39.330us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 5.000s | 14.694us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 4.000s | 25.376us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 43.000s | 4950.623us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 17.000s | 374.534us | 5 | 5 | 100.00 |
| V1 | TOTAL | 166 | 166 | 100.00 | |||
| V2 | reset_recovery | otbn_reset | 41.000s | 184.449us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 48.000s | 639.863us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 561.000s | 1972.702us | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 112.000s | 333.939us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 74.000s | 312.425us | 59 | 60 | 98.33 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 12.000s | 24.994us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 217.000s | 821.142us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 7.000s | 33.180us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 6.000s | 23.600us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 7.000s | 617.673us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 7.000s | 617.673us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 6.000s | 23.705us | 5 | 5 | 100.00 |
| otbn_csr_rw | 5.000s | 14.694us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 4.000s | 25.376us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 10.000s | 47.001us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 6.000s | 23.705us | 5 | 5 | 100.00 |
| otbn_csr_rw | 5.000s | 14.694us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 4.000s | 25.376us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 10.000s | 47.001us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 245 | 246 | 99.59 | |||
| V2S | mem_integrity | otbn_imem_err | 20.000s | 62.914us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.158s | 0.000us | 14 | 15 | 93.33 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 16.000s | 40.946us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 15.000s | 71.938us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 95.000s | 1750.647us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 9.000s | 39.701us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 9.000s | 17.701us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 10.000s | 39.653us | 2 | 2 | 100.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 10.000s | 42.285us | 10 | 10 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 |
| otbn_tl_intg_err | 30.000s | 181.452us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 36.000s | 243.948us | 16 | 20 | 80.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 |
| V2S | prim_count_check | otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 12.000s | 40.237us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 14.158s | 0.000us | 14 | 15 | 93.33 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 20.000s | 62.914us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 30.000s | 181.452us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 74.000s | 312.425us | 59 | 60 | 98.33 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 20.000s | 62.914us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.158s | 0.000us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 12.000s | 24.994us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 9.000s | 17.701us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 391.000s | 1291.917us | 100 | 100 | 100.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 20.000s | 62.914us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.158s | 0.000us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 12.000s | 24.994us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 9.000s | 17.701us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 74.000s | 312.425us | 59 | 60 | 98.33 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 20.000s | 62.914us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.158s | 0.000us | 14 | 15 | 93.33 | ||
| otbn_zero_state_err_urnd | 12.000s | 24.994us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 9.000s | 17.701us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 391.000s | 1291.917us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 11.000s | 634.873us | 11 | 12 | 91.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 11.360s | 0.000us | 4 | 5 | 80.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 115.000s | 1065.677us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 115.000s | 1065.677us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 12.000s | 21.534us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 14.000s | 58.442us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 12.000s | 109.035us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 12.000s | 109.035us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 10.000s | 25.041us | 5 | 7 | 71.43 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 391.000s | 1291.917us | 100 | 100 | 100.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 391.000s | 1291.917us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 391.000s | 1291.917us | 100 | 100 | 100.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 561.000s | 1972.702us | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 391.000s | 1291.917us | 100 | 100 | 100.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 391.000s | 1291.917us | 100 | 100 | 100.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 11.000s | 32.936us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 391.000s | 1291.917us | 100 | 100 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 480.000s | 2168.791us | 2 | 5 | 40.00 |
| V2S | TOTAL | 151 | 163 | 92.64 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 349.000s | 1202.229us | 1 | 10 | 10.00 |
| V3 | TOTAL | 1 | 10 | 10.00 | |||
| TOTAL | 563 | 585 | 96.24 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.95 | 99.56 | 94.71 | 99.65 | 92.93 | 93.66 | 97.44 | 89.83 | 99.57 |
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
0.otbn_stress_all_with_rand_reset.111029925396449038868615722214261310235666612088029329153408504899485068725950
Line 226, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1338714960 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1338714960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.otbn_stress_all_with_rand_reset.25450593356339769021589985998345575246517530667326809881309355015929326604912
Line 157, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 124991217 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 124991217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:
Test otbn_ctrl_redun has 1 failures.
3.otbn_ctrl_redun.69558979368212540691776995194181319686660189511180894256085585236114665967674
Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 10921403 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 10921403 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 10921403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_sec_wipe_err has 2 failures.
4.otbn_sec_wipe_err.2742315741614325434046041657430313520354587146050396706519335521289492857914
Line 112, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 95380128 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 95380128 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 95380128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.otbn_sec_wipe_err.14855563411269641493300928835454385623723156191926674486252541245916457886627
Line 109, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/5.otbn_sec_wipe_err/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19196643 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 19196643 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 19196643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 1 failures.
53.otbn_escalate.94966623465034989242104036237170978908017247183703215826605563462896773422095
Line 117, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/53.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 14939041 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 14939041 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 14939041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 3 failures:
0.otbn_sec_cm.54105259722246318153184188092287223303887114021451796910495545018392290551558
Line 97, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 200778316 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 200778316 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 200778316 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 200778316 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 200778316 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
1.otbn_sec_cm.63010121826617483802813290934214162036408309385685599236278789336341602883575
Line 110, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 142683791 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 142683791 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 142683791 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 142683791 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 142683791 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
... and 1 more failures.
Job returned non-zero exit code has 2 failures:
Test otbn_dmem_err has 1 failures.
0.otbn_dmem_err.57014705757182616739622822430153681842490062256246031560552493727877204291576
Log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/run.log
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 57014705757182616739622822430153681842490062256246031560552493727877204291576 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest run_opts='+otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=3440914424 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_dmem_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_dmem_err.3440914424 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_dmem_err.3440914424 -covoverwrite' seed=57014705757182616739622822430153681842490062256246031560552493727877204291576 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_dmem_err_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 57014705757182616739622822430153681842490062256246031560552493727877204291576 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest
2025/11/29 06:30:21 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
Test otbn_pc_ctrl_flow_redun has 1 failures.
0.otbn_pc_ctrl_flow_redun.53112500535719906114824736926136664087702097703343242140934000130518285813656
Log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest/run.log
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 53112500535719906114824736926136664087702097703343242140934000130518285813656 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest run_opts='+otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=3899131800 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_pc_ctrl_flow_redun_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_pc_ctrl_flow_redun.3899131800 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_pc_ctrl_flow_redun.3899131800 -covoverwrite' seed=53112500535719906114824736926136664087702097703343242140934000130518285813656 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_pc_ctrl_flow_redun_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 53112500535719906114824736926136664087702097703343242140934000130518285813656 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest
2025/11/29 06:30:22 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
0.otbn_passthru_mem_tl_intg_err.88526341812419459505634245952614788851520881567354660505694450008033837672954
Line 93, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 24886339 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 24886339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_passthru_mem_tl_intg_err.17442514890106937404558118211179717355431366104800178119068940765483620367677
Line 88, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 19912162 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 19912162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 2 failures:
1.otbn_passthru_mem_tl_intg_err.85921269373206494911238619742304099614377784347335021897698234788185410159371
Line 83, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 1926865 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1926865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.otbn_passthru_mem_tl_intg_err.3087751644925730517841657604592917979240017963384223063502119011319347707666
Line 88, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/9.otbn_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 11249260 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 11249260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
6.otbn_stress_all_with_rand_reset.1650868231975063570051687310912280255311788472706005247223343123164384543408
Line 192, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 281363706 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 281363706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---