ROM_CTRL/32KB Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: 1ac1583

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.470s	182.886us	4	4	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.370s	239.238us	10	10	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.440s	1032.750us	40	40	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.560s	296.164us	10	10	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.260s	216.632us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	12.120s	4137.303us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.440s	1032.750us	40	40	100.00
		rom_ctrl_csr_aliasing	10.260s	216.632us	10	10	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.980s	292.867us	10	10	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.010s	300.118us	10	10	100.00
V1		TOTAL			134	134	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	12.950s	298.373us	4	4	100.00
V2	stress_all	rom_ctrl_stress_all	52.300s	22829.274us	40	40	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	21.550s	567.855us	4	4	100.00
V2	alert_test	rom_ctrl_alert_test	12.000s	302.834us	100	100	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.700s	1036.618us	40	40	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.700s	1036.618us	40	40	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.370s	239.238us	10	10	100.00
		rom_ctrl_csr_rw	15.440s	1032.750us	40	40	100.00
		rom_ctrl_csr_aliasing	10.260s	216.632us	10	10	100.00
		rom_ctrl_same_csr_outstanding	14.950s	999.329us	40	40	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.370s	239.238us	10	10	100.00
		rom_ctrl_csr_rw	15.440s	1032.750us	40	40	100.00
		rom_ctrl_csr_aliasing	10.260s	216.632us	10	10	100.00
		rom_ctrl_same_csr_outstanding	14.950s	999.329us	40	40	100.00
V2		TOTAL			228	228	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	227.330s	38027.915us	36	40	90.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	57.230s	6099.043us	40	40	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	568.360s	1061.808us	2	10	20.00
		rom_ctrl_tl_intg_err	137.310s	1239.881us	40	40	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	568.360s	1061.808us	2	10	20.00
V2S	prim_count_check	rom_ctrl_sec_cm	568.360s	1061.808us	2	10	20.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	227.330s	38027.915us	36	40	90.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	227.330s	38027.915us	36	40	90.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	227.330s	38027.915us	36	40	90.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	227.330s	38027.915us	36	40	90.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	227.330s	38027.915us	36	40	90.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	568.360s	1061.808us	2	10	20.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	568.360s	1061.808us	2	10	20.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.470s	182.886us	4	4	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.470s	182.886us	4	4	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.470s	182.886us	4	4	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	137.310s	1239.881us	40	40	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	227.330s	38027.915us	36	40	90.00
		rom_ctrl_kmac_err_chk	21.550s	567.855us	4	4	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	227.330s	38027.915us	36	40	90.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	227.330s	38027.915us	36	40	90.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	227.330s	38027.915us	36	40	90.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	57.230s	6099.043us	40	40	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	568.360s	1061.808us	2	10	20.00
V2S		TOTAL			118	130	90.77
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	496.650s	18733.742us	40	40	100.00
V3		TOTAL			40	40	100.00
		TOTAL			520	532	97.74

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.29	99.46	95.39	99.59	100.00	99.27	95.49	98.81

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 4 failures:
  • Test rom_ctrl_sec_cm has 4 failures.

    • 0.rom_ctrl_sec_cm.115196415441044276716223838476428896853256828159441435164045878691541115712518
      Line 289, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 44535106ps failed at 44535106ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 44535106ps failed at 44535106ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 1.rom_ctrl_sec_cm.8846467202509625646362721204326130472821906850203892785054422645355274068374
      Line 245, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 121488087ps failed at 121488087ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 121488087ps failed at 121488087ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • ... and 2 more failures.

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 4 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 4 failures.

    • 2.rom_ctrl_corrupt_sig_fatal_chk.37071611271128195316049204561508953373575578463964352240707461912939070964675
      Line 86, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 860685733 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 860685733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.rom_ctrl_corrupt_sig_fatal_chk.57532051891555783196794139767705363921513916068447307134374884849571377607672
      Line 93, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 475443705 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 475443705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 4 failures:
  • Test rom_ctrl_sec_cm has 4 failures.

    • 2.rom_ctrl_sec_cm.51613485082782862581977431920671952919738976725645837303334383243023762846480
      Line 167, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 28337207ps failed at 28337207ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 28375669ps failed at 28375669ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
      

    • 4.rom_ctrl_sec_cm.2589119975370618989133849552306216063704922993874804028676506438798061204813
      Line 177, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 38434423ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 38434423ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 38434423ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

    • ... and 2 more failures.