RV_TIMER Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: `1ac1583`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.430s	691.069us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.900s	13.506us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	1.040s	13.573us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.590s	87.935us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.010s	14.789us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.390s	111.906us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.040s	13.573us	20	20	100.00
		rv_timer_csr_aliasing	1.010s	14.789us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	2.600s	1437.916us	2	20	10.00
V2	disabled	rv_timer_disabled	2.950s	1189.229us	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	804.940s	607730.769us	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	804.940s	607730.769us	10	10	100.00
V2	stress	rv_timer_stress_all	4.630s	3132.831us	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.820s	34.619us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.970s	18.104us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.510s	191.439us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.510s	191.439us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.900s	13.506us	5	5	100.00
		rv_timer_csr_rw	1.040s	13.573us	20	20	100.00
		rv_timer_csr_aliasing	1.010s	14.789us	5	5	100.00
		rv_timer_same_csr_outstanding	1.150s	27.423us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.900s	13.506us	5	5	100.00
		rv_timer_csr_rw	1.040s	13.573us	20	20	100.00
		rv_timer_csr_aliasing	1.010s	14.789us	5	5	100.00
		rv_timer_same_csr_outstanding	1.150s	27.423us	20	20	100.00
V2		TOTAL			192	210	91.43
V2S	tl_intg_err	rv_timer_sec_cm	1.280s	171.615us	5	5	100.00
		rv_timer_tl_intg_err	1.680s	318.479us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.680s	318.479us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.840s	229.176us	1	10	10.00
V3	max_value	rv_timer_max	0.900s	49.705us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	39.740s	7140.530us	17	20	85.00
V3		TOTAL			18	40	45.00
		TOTAL			310	350	88.57

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.22	100.00	100.00	100.00	--	100.00	96.82	98.53

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 27 failures:
- Test rv_timer_random_reset has 18 failures.
  - 0.rv_timer_random_reset.87458374657173798298558161593033926416453275996709819147326922270023890462308
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 455478095 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x1af58504) == 0x1
  UVM_INFO @ 455478095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.20153967505522416205136516794784479124674087475838871771283386861768547544348
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 419847635 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x66d2f504) == 0x1
  UVM_INFO @ 419847635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.
- Test rv_timer_min has 9 failures.
  - 1.rv_timer_min.32820118321139108264103662929908793176235382003884744014526355521810262220624
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
```
  UVM_FATAL @  61160393 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd670a304) == 0x1
  UVM_INFO @  61160393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.rv_timer_min.12804638304624199066166025913748235429408262180263856198681688089379768455155
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 569963550 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x90861f04) == 0x1
  UVM_INFO @ 569963550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 10 failures:
- Test rv_timer_max has 10 failures.
  - 0.rv_timer_max.7291363229088604281199535944049092472625487927506972412761371772636352483548
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @  49704552 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  49704552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.87478436572193267383383296875103506158831956645787941220839621949917591815460
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @  69083119 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  69083119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test rv_timer_stress_all_with_rand_reset has 2 failures.

8.rv_timer_stress_all_with_rand_reset.84102110453315026549598435651632361911763576487512170843299530363113146016352
Line 114, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/8.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 124184432 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 124184432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.rv_timer_stress_all_with_rand_reset.108590051301121570018030730244548733127641055219288022029581727387994383355701
Line 253, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/15.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 22629571700 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 22629571700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 1.rv_timer_stress_all_with_rand_reset.46797188524762797589220582065643051724375410484760691468633737499413090928167
    Line 122, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 904087111 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 904087111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```