SPI_DEVICE/1R1W Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: 1ac1583

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	639.960s	92445.491us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.700s	302.221us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.970s	564.408us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	31.750s	2791.944us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	18.020s	1100.918us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.940s	134.497us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.970s	564.408us	20	20	100.00
		spi_device_csr_aliasing	18.020s	1100.918us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.040s	13.314us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.030s	21.864us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.170s	22.810us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.070s	1.621us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.010s	3.808us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	6.730s	148.016us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.730s	148.016us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.350s	7219.899us	50	50	100.00
		spi_device_tpm_sts_read	1.480s	139.754us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	36.350s	34107.527us	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	24.860s	5591.651us	50	50	100.00
		spi_device_flash_all	1456.970s	1500000.000us	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	39.860s	13150.088us	50	50	100.00
		spi_device_flash_all	1456.970s	1500000.000us	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	39.860s	13150.088us	50	50	100.00
		spi_device_flash_all	1456.970s	1500000.000us	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	1456.970s	1500000.000us	49	50	98.00
V2	cmd_read_status	spi_device_intercept	25.720s	3369.175us	50	50	100.00
		spi_device_flash_all	1456.970s	1500000.000us	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	25.720s	3369.175us	50	50	100.00
		spi_device_flash_all	1456.970s	1500000.000us	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	25.720s	3369.175us	50	50	100.00
		spi_device_flash_all	1456.970s	1500000.000us	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	25.720s	3369.175us	50	50	100.00
		spi_device_flash_all	1456.970s	1500000.000us	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	25.720s	3369.175us	50	50	100.00
		spi_device_flash_all	1456.970s	1500000.000us	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	34.670s	39732.246us	50	50	100.00
V2	mailbox_command	spi_device_mailbox	128.110s	60133.514us	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	128.110s	60133.514us	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	128.110s	60133.514us	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	40.280s	7343.346us	50	50	100.00
		spi_device_read_buffer_direct	14.800s	1454.272us	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	128.110s	60133.514us	50	50	100.00
		spi_device_flash_all	1456.970s	1500000.000us	49	50	98.00
V2	quad_spi	spi_device_flash_all	1456.970s	1500000.000us	49	50	98.00
V2	dual_spi	spi_device_flash_all	1456.970s	1500000.000us	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.660s	10170.282us	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	24.660s	10170.282us	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	639.960s	92445.491us	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	307.160s	43814.598us	49	50	98.00
V2	stress_all	spi_device_stress_all	795.720s	417257.903us	49	50	98.00
V2	alert_test	spi_device_alert_test	1.100s	20.645us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.140s	32.518us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.420s	341.340us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.420s	341.340us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.700s	302.221us	5	5	100.00
		spi_device_csr_rw	2.970s	564.408us	20	20	100.00
		spi_device_csr_aliasing	18.020s	1100.918us	5	5	100.00
		spi_device_same_csr_outstanding	4.750s	2664.533us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.700s	302.221us	5	5	100.00
		spi_device_csr_rw	2.970s	564.408us	20	20	100.00
		spi_device_csr_aliasing	18.020s	1100.918us	5	5	100.00
		spi_device_same_csr_outstanding	4.750s	2664.533us	20	20	100.00
V2		TOTAL			937	961	97.50
V2S	tl_intg_err	spi_device_sec_cm	1.700s	186.459us	5	5	100.00
		spi_device_tl_intg_err	22.350s	3595.008us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.350s	3595.008us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	432.230s	83287.602us	49	50	98.00
		TOTAL			1126	1151	97.83

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.38	99.11	96.58	83.54	89.36	98.40	94.43	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.19550660912523369832618490001852550380035711563383952101786627319826707864711
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1127286 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[85])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1127286 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1127286 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[981])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.53324140945230538284993837201953410596124734949228871365103216545377212223540
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3625345 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[62])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3625345 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3625345 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[958])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 2 failures:

  • Test spi_device_flash_and_tpm_min_idle has 1 failures.

    • 10.spi_device_flash_and_tpm_min_idle.44837572089202246684891099151346778256043014189814854613305204754260545480627
      Line 78, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest/run.log

        UVM_ERROR @ 505520578 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (13254656 [0xca4000] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xca4000 != exp 0x0
        tl_ul_fuzzy_flash_status_q[i] = 0x80828
        UVM_INFO @ 613558578 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/7
        UVM_INFO @ 613558578 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/7
        tl_ul_fuzzy_flash_status_q[i] = 0x80828
      

  • Test spi_device_stress_all has 1 failures.

    • 40.spi_device_stress_all.24556861893620751594963044784244103355744538079962144537005456981398557834896
      Line 140, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest/run.log

        UVM_ERROR @ 210801964462 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (14652416 [0xdf9400] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xdf9400 != exp 0x0
        tl_ul_fuzzy_flash_status_q[i] = 0xc1ee28
        tl_ul_fuzzy_flash_status_q[i] = 0x80e41e
        UVM_INFO @ 211848312325 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/11
        UVM_INFO @ 211848312325 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/11
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.60898828098628222650026785308000571771571892894141649394562230235826488042791
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1079145 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x37aa96 [1101111010101010010110] vs 0x0 [0])
        UVM_ERROR @   1165145 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa9e384 [101010011110001110000100] vs 0x0 [0])
        UVM_ERROR @   1173145 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe9a910 [111010011010100100010000] vs 0x0 [0])
        UVM_ERROR @   1234145 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9c6582 [100111000110010110000010] vs 0x0 [0])
        UVM_ERROR @   1317145 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9150eb [100100010101000011101011] vs 0x0 [0])
      

• UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 9.spi_device_flash_mode_ignore_cmds.58841708939855755852733072219738187276583778342511843926822037334272391099733
      Line 90, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 8826063977 ps: (spi_device_pass_base_vseq.sv:705) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        UVM_INFO @ 11820283977 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 3/5
        UVM_INFO @ 11820283977 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 4/5
        tl_ul_fuzzy_flash_status_q[i] = 0x332054
        tl_ul_fuzzy_flash_status_q[i] = 0x4017a8
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_device_flash_all has 1 failures.

    • 48.spi_device_flash_all.14568690040855799601958310748581242988863014086313237913136145428088600600662
      Line 91, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest/run.log

        UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---