SPI_HOST Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: 1ac1583

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	93.000s	9407.475us	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	22.447us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	19.781us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	160.941us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	49.062us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	67.449us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	19.781us	20	20	100.00
		spi_host_csr_aliasing	2.000s	49.062us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	23.982us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	61.511us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	2.000s	21.577us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	23.000s	530.287us	50	50	100.00
		spi_host_error_cmd	2.000s	28.331us	50	50	100.00
		spi_host_event	570.000s	25021.135us	50	50	100.00
V2	clock_rate	spi_host_speed	8.000s	286.578us	50	50	100.00
V2	speed	spi_host_speed	8.000s	286.578us	50	50	100.00
V2	chip_select_timing	spi_host_speed	8.000s	286.578us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	136.000s	6623.088us	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	26.898us	50	50	100.00
V2	cpol_cpha	spi_host_speed	8.000s	286.578us	50	50	100.00
V2	full_cycle	spi_host_speed	8.000s	286.578us	50	50	100.00
V2	duplex	spi_host_smoke	93.000s	9407.475us	50	50	100.00
V2	tx_rx_only	spi_host_smoke	93.000s	9407.475us	50	50	100.00
V2	stress_all	spi_host_stress_all	85.000s	7720.716us	50	50	100.00
V2	spien	spi_host_spien	242.000s	32039.393us	50	50	100.00
V2	stall	spi_host_status_stall	2088.000s	675206.448us	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	43.000s	8904.678us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	23.000s	530.287us	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	26.060us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	19.293us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	574.585us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	574.585us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	22.447us	5	5	100.00
		spi_host_csr_rw	2.000s	19.781us	20	20	100.00
		spi_host_csr_aliasing	2.000s	49.062us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	61.323us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	22.447us	5	5	100.00
		spi_host_csr_rw	2.000s	19.781us	20	20	100.00
		spi_host_csr_aliasing	2.000s	49.062us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	61.323us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	tl_intg_err	spi_host_sec_cm	2.000s	217.267us	5	5	100.00
		spi_host_tl_intg_err	3.000s	937.926us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	937.926us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	493.000s	59718.416us	10	10	100.00
		TOTAL			839	840	99.88

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.16	96.82	93.35	98.69	94.25	88.02	100.00	95.21	90.42

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: * has 1 failures:
  • Test spi_host_status_stall has 1 failures.

    • 42.spi_host_status_stall.35332895724861048120835390870727773013467562451988597631640220301723889839437
      Line 3669, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/42.spi_host_status_stall/latest/run.log

        UVM_ERROR @ 11084405961 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0
        UVM_INFO @ 11084405961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---