SRAM_CTRL/RET Simulation Results

Friday November 28 2025 17:08:43 UTC

GitHub Revision: `1ac1583`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	107.360s	650.688us	100	100	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.040s	19.648us	10	10	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.060s	222.346us	40	40	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	4.260s	3297.889us	10	10	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.110s	21.742us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.140s	2516.124us	38	40	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.060s	222.346us	40	40	100.00
		sram_ctrl_csr_aliasing	1.110s	21.742us	10	10	100.00
V1	mem_walk	sram_ctrl_mem_walk	353.190s	21581.475us	100	100	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	208.800s	8786.140us	100	100	100.00
V1		TOTAL			408	410	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	1495.540s	66068.134us	100	100	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	432.200s	96492.742us	100	100	100.00
V2	bijection	sram_ctrl_bijection	2825.030s	1067280.844us	100	100	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1829.120s	231191.992us	100	100	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	157.620s	113124.187us	100	100	100.00
V2	executable	sram_ctrl_executable	1704.690s	271975.324us	100	100	100.00
V2	partial_access	sram_ctrl_partial_access	108.090s	208.917us	100	100	100.00
		sram_ctrl_partial_access_b2b	601.980s	523013.724us	100	100	100.00
V2	max_throughput	sram_ctrl_max_throughput	100.430s	136.265us	100	100	100.00
		sram_ctrl_throughput_w_partial_write	109.870s	817.813us	100	100	100.00
		sram_ctrl_throughput_w_readback	112.360s	1940.296us	100	100	100.00
V2	regwen	sram_ctrl_regwen	1205.200s	53625.202us	100	100	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.690s	2414.924us	100	100	100.00
V2	stress_all	sram_ctrl_stress_all	6853.260s	341107.215us	100	100	100.00
V2	alert_test	sram_ctrl_alert_test	1.090s	31.832us	100	100	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.020s	489.144us	40	40	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.020s	489.144us	40	40	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.040s	19.648us	10	10	100.00
		sram_ctrl_csr_rw	1.060s	222.346us	40	40	100.00
		sram_ctrl_csr_aliasing	1.110s	21.742us	10	10	100.00
		sram_ctrl_same_csr_outstanding	1.160s	199.450us	40	40	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.040s	19.648us	10	10	100.00
		sram_ctrl_csr_rw	1.060s	222.346us	40	40	100.00
		sram_ctrl_csr_aliasing	1.110s	21.742us	10	10	100.00
		sram_ctrl_same_csr_outstanding	1.160s	199.450us	40	40	100.00
V2		TOTAL			1580	1580	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	73.750s	73800.590us	40	40	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.980s	3.590us	0	10	0.00
		sram_ctrl_tl_intg_err	3.590s	1692.120us	40	40	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.980s	3.590us	0	10	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.590s	1692.120us	40	40	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1205.200s	53625.202us	100	100	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1205.200s	53625.202us	100	100	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.060s	222.346us	40	40	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1704.690s	271975.324us	100	100	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1704.690s	271975.324us	100	100	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1704.690s	271975.324us	100	100	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	157.620s	113124.187us	100	100	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	11.490s	6727.340us	88	100	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	73.750s	73800.590us	40	40	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	9.970s	4773.897us	70	100	70.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	107.360s	650.688us	100	100	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	107.360s	650.688us	100	100	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1704.690s	271975.324us	100	100	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.980s	3.590us	0	10	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	157.620s	113124.187us	100	100	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.980s	3.590us	0	10	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.980s	3.590us	0	10	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	107.360s	650.688us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.980s	3.590us	0	10	0.00
V2S		TOTAL			238	290	82.07
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	921.680s	4144.018us	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			2325	2380	97.69

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.36	99.07	92.90	90.66	100.00	97.98	95.79	98.14

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 29 failures:
- Test sram_ctrl_readback_err has 29 failures.
  - 1.sram_ctrl_readback_err.76330011312018798801960369668789959961362699504448647382976434175409556736105
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 2632105678 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x34) != exp (0x43)
  UVM_INFO @ 2632105678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.sram_ctrl_readback_err.86252051900889855639709426890929812213198949147647951247512698024526178094752
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 657740538 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x49) != exp (0x44)
  UVM_INFO @ 657740538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 27 more failures.
Offending 'reqfifo_rvalid' has 12 failures:
- Test sram_ctrl_mubi_enc_err has 12 failures.
  - 1.sram_ctrl_mubi_enc_err.73611958379093058187521990965520859974854819125827672713173803210186928205383
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 678415698 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 678415698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.sram_ctrl_mubi_enc_err.101277718349595393759862046078264120797522980547412001628019725498941400351392
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 9432602902 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 9432602902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 9 failures:
- Test sram_ctrl_sec_cm has 9 failures.
  - 0.sram_ctrl_sec_cm.107086841652185793439905334931932143778053670840656131872776820241136769193626
    Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @  13717794 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  13717794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.sram_ctrl_sec_cm.70785049387823633726053235396158876459348710336599397974486646700462615397132
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   3150805 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   3150805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 4.sram_ctrl_csr_mem_rw_with_rand_reset.96543689193997880061617103467127812997721367191482541405963391177987797097327
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  22647091 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  22647091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 14.sram_ctrl_csr_mem_rw_with_rand_reset.92375685363562665262480053080328672725285266215117671484815673334881375245769
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  22895378 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  22895378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 3.sram_ctrl_sec_cm.77126030049714401713576866922640050852613414388572762611298433880615036453104
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   4348121 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   4348121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3710) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_readback_err has 1 failures.

38.sram_ctrl_readback_err.12807720880482777619005672566596874715429140135050845375192379266725261913233
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/38.sram_ctrl_readback_err/latest/run.log

  UVM_ERROR @ 125425168 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3710) { a_addr: 'h18825aec  a_data: 'h33  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h0  a_user: 'h26168  d_param: 'h0  d_source: 'h2e  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 125425168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 44.sram_ctrl_stress_all_with_rand_reset.64859132145990723873194352429011803875294518397168368757871729839595834473374
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1767641204 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1767641204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```