1ac1583| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 131.605s | 0.000us | 0 | 5 | 0.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 131.605s | 0.000us | 0 | 5 | 0.00 |
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 97.466s | 0.000us | 0 | 20 | 0.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 104.785s | 0.000us | 0 | 5 | 0.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 394.220s | 271.872us | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 394.220s | 271.872us | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 394.220s | 271.872us | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_rom | 32.010s | 10.340us | 0 | 3 | 0.00 |
| chip_sw_example_manufacturer | 161.952s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_example_concurrency | 259.230s | 150.398us | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 33.185s | 0.000us | 0 | 3 | 0.00 | ||
| V1 | csr_bit_bash | chip_csr_bit_bash | 12.040s | 0.000us | 0 | 3 | 0.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 15.380s | 0.000us | 0 | 3 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 15.380s | 0.000us | 0 | 3 | 0.00 |
| V1 | xbar_smoke | xbar_smoke | 37.340s | 70.061us | 100 | 100 | 100.00 |
| V1 | TOTAL | 106 | 151 | 70.20 | |||
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 125.579s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 3101.320s | 3795.584us | 2 | 3 | 66.67 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 384.850s | 291.732us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 96.437s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 127.360s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 95.485s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 88.408s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 4.300s | 0.000us | 0 | 10 | 0.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 4.300s | 0.000us | 0 | 10 | 0.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 153.763s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 141.337s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 155.138s | 0.000us | 0 | 6 | 0.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 155.138s | 0.000us | 0 | 6 | 0.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 152.970s | 117.043us | 0 | 3 | 0.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 157.020s | 117.021us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 328.130s | 272.822us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 14.487s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 15.148s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 737.710s | 897.785us | 0 | 3 | 0.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 311.070s | 248.724us | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 588.620s | 589.558us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 588.620s | 589.558us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 464.360s | 348.575us | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 255.950s | 164.337us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 255.950s | 164.337us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 400.240s | 2271.469us | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 201.280s | 145.506us | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 366.190s | 225.687us | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 236.720s | 147.280us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 259.960s | 161.552us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 205.990s | 145.027us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 212.980s | 165.632us | 0 | 3 | 0.00 |
| chip_sw_clkmgr_off_hmac_trans | 231.060s | 165.616us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 230.630s | 165.664us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 214.150s | 165.680us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_otbn_ecdsa_op_irq_jitter_en | 63.660s | 10.400us | 0 | 3 | 0.00 |
| chip_sw_aes_enc_jitter_en | 45.300s | 10.360us | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en | 49.010s | 10.320us | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 48.640s | 10.180us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 52.530s | 10.400us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 18.662s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_jitter | 194.300s | 141.884us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 441.370s | 1779.359us | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 62.620s | 10.340us | 0 | 3 | 0.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 53.490s | 10.180us | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 52.820s | 10.340us | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 58.860s | 10.140us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 63.260s | 10.340us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 56.990s | 10.300us | 0 | 3 | 0.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 55.900s | 10.220us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 17.659s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 16.797s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 19.549s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 1458.190s | 905.717us | 0 | 100 | 0.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 480.440s | 504.445us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 255.950s | 164.337us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 16.953s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 480.440s | 504.445us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 15.282s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 96.059s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 62.733s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 18.313s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 26.535s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 1458.190s | 905.717us | 0 | 100 | 0.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 328.130s | 272.822us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 446.070s | 375.296us | 0 | 3 | 0.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 393.440s | 267.540us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 386.940s | 289.922us | 0 | 3 | 0.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 195.290s | 144.094us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 1458.190s | 905.717us | 0 | 100 | 0.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 14.789s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 13.843s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 1458.190s | 905.717us | 0 | 100 | 0.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 15.689s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 386.940s | 289.922us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 434.140s | 398.562us | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 32.589s | 0.000us | 0 | 90 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 15.442s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 15.137s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 14.358s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 16.037s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 13.843s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_sw_lc_ctrl_transition | 31.888s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 68.586s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 31.888s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 31.888s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 31.888s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_dpe_key_derivation_prod | 348.020s | 267.792us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_prim_tl_access | 623.140s | 856.074us | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 737.710s | 897.785us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 60.205s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 75.027s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 49.195s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 28.733s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_ctrl_transition | 31.888s | 0.000us | 0 | 15 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation | 351.400s | 267.820us | 0 | 3 | 0.00 | ||
| chip_sw_rom_ctrl_integrity_check | 1139.760s | 1266.526us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 15.038s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 230.940s | 157.156us | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 45.300s | 10.360us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 237.480s | 145.829us | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 236.720s | 147.280us | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 222.180s | 156.410us | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 49.010s | 10.320us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 259.960s | 161.552us | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 239.690s | 148.913us | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 268.000s | 172.127us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 52.530s | 10.400us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_dpe_key_derivation | 351.400s | 267.820us | 0 | 3 | 0.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 31.888s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 51.110s | 10.160us | 0 | 3 | 0.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 322.130s | 195.656us | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 205.990s | 145.027us | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 494.900s | 298.122us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 494.900s | 298.122us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 17.364s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 267.390s | 156.758us | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 4098.750s | 2307.012us | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_dpe_key_derivation | chip_sw_keymgr_dpe_key_derivation | 351.400s | 267.820us | 0 | 3 | 0.00 |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 48.640s | 10.180us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 3862.700s | 1473.437us | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 63.660s | 10.400us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 366.190s | 225.687us | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 366.190s | 225.687us | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 366.190s | 225.687us | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 491.600s | 265.177us | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 1139.760s | 1266.526us | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 1139.760s | 1266.526us | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 445.040s | 314.094us | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 18.662s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 15.038s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 1458.190s | 905.717us | 0 | 100 | 0.00 |
| chip_sw_data_integrity_escalation | 155.138s | 0.000us | 0 | 6 | 0.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 31.888s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_otbn_mem_scramble | 491.600s | 265.177us | 3 | 3 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 351.400s | 267.820us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 445.040s | 314.094us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 203.870s | 161.424us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_otbn_mem_scramble | 491.600s | 265.177us | 3 | 3 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 351.400s | 267.820us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 445.040s | 314.094us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 203.870s | 161.424us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 31.888s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 15.202s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 68.586s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_prim_tl_access | 623.140s | 856.074us | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 60.205s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 75.027s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 49.195s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 28.733s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_ctrl_transition | 31.888s | 0.000us | 0 | 15 | 0.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 623.140s | 856.074us | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_nvm_cnt | chip_sw_otp_ctrl_nvm_cnt | 42.194s | 0.000us | 0 | 1 | 0.00 |
| V2 | chip_sw_otp_ctrl_sw_parts | chip_sw_otp_ctrl_sw_parts | 45.512s | 0.000us | 0 | 1 | 0.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 17.659s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_otbn_ecdsa_op_irq_jitter_en | 63.660s | 10.400us | 0 | 3 | 0.00 |
| chip_sw_aes_enc_jitter_en | 45.300s | 10.360us | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en | 49.010s | 10.320us | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 48.640s | 10.180us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 52.530s | 10.400us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 18.662s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_jitter | 194.300s | 141.884us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_soc_proxy_external_reset_requests | chip_sw_soc_proxy_smoketest | 221.300s | 143.472us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_external_irqs | chip_sw_soc_proxy_smoketest | 221.300s | 143.472us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_external_wakeup_requests | chip_sw_soc_proxy_external_wakeup | 216.070s | 138.776us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_gpios | chip_sw_soc_proxy_gpios | 207.470s | 136.454us | 0 | 3 | 0.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 471.440s | 251.539us | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 321.150s | 193.997us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 247.820s | 164.788us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 203.870s | 161.424us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 446.070s | 375.296us | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 446.070s | 375.296us | 0 | 3 | 0.00 |
| V2 | chip_sw_smoketest | chip_sw_aes_smoketest | 225.470s | 157.084us | 3 | 3 | 100.00 |
| chip_sw_aon_timer_smoketest | 246.570s | 163.303us | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 206.880s | 142.931us | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 207.770s | 144.825us | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 215.330s | 165.754us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 268.550s | 182.035us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 254.130s | 171.089us | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 313.510s | 220.790us | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 197.740s | 146.964us | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 202.570s | 145.071us | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 314.880s | 248.732us | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 208.500s | 141.601us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 218.590s | 145.507us | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 221.320s | 157.720us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 44.338s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 33.185s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 125.579s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_secure_boot | base_rom_e2e_smoke | 15.852s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 233.190s | 203.702us | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 222.930s | 215.274us | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 228.150s | 227.275us | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 233.740s | 221.441us | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_rv_dm_lc_disabled | 737.710s | 897.785us | 0 | 3 | 0.00 |
| chip_sw_lc_walkthrough_testunlocks | 22.382s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 17.949s | 0.000us | 0 | 3 | 0.00 |
| chip_sw_lc_walkthrough_prod | 43.887s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_prodend | 22.357s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_rma | 20.417s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 22.382s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 863.670s | 778.516us | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 758.880s | 789.024us | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 73.354s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 14.800s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 158.501s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 167.771s | 0.000us | 0 | 3 | 0.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 171.140s | 118.071us | 0 | 30 | 0.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 171.140s | 118.071us | 0 | 30 | 0.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 15.380s | 0.000us | 0 | 3 | 0.00 |
| chip_same_csr_outstanding | 14.920s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 15.380s | 0.000us | 0 | 3 | 0.00 |
| chip_same_csr_outstanding | 14.920s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 326.800s | 521.341us | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 15.420s | 12.929us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 646.480s | 2721.481us | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 754.010s | 2336.545us | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 142.870s | 84.123us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 2341.820s | 13437.314us | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 3475.760s | 14182.301us | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 177.910s | 206.757us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 171.470s | 214.907us | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 328.270s | 533.384us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 171.470s | 214.907us | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 557.020s | 949.154us | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 3528.430s | 16357.995us | 72 | 100 | 72.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 256.780s | 474.486us | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 2125.450s | 4005.174us | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 1736.120s | 3506.804us | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 3486.900s | 5642.812us | 97 | 100 | 97.00 |
| xbar_stress_all_with_reset_error | 3507.390s | 5285.837us | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 15.451s | 0.000us | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 15.516s | 0.000us | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 15.275s | 0.000us | 0 | 3 | 0.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 12.644s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 12.589s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 12.768s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 13.737s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 14.281s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 12.371s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 14.646s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 12.308s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 13.928s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 12.430s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 89.701s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 90.652s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 78.314s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 79.154s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 96.028s | 0.000us | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 59.661s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 93.205s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 87.012s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 89.637s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 76.852s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 75.678s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 65.211s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 65.362s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 69.159s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 65.186s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 13.988s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 28.295s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 13.254s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 15.783s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 11.295s | 0.000us | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 18.476s | 0.000us | 0 | 3 | 0.00 |
| rom_e2e_asm_init_dev | 16.299s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod | 22.082s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod_end | 18.143s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_rma | 15.868s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 15.844s | 0.000us | 0 | 3 | 0.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 14.572s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 14.186s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 15.419s | 0.000us | 0 | 3 | 0.00 |
| V2 | TOTAL | 1823 | 2405 | 75.80 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 276.260s | 173.872us | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 189.370s | 126.520us | 3 | 3 | 100.00 |
| V2S | TOTAL | 6 | 6 | 100.00 | |||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 15.476s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 18.732s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 15.001s | 0.000us | 0 | 1 | 0.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 15.260s | 0.000us | 0 | 3 | 0.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 1458.190s | 905.717us | 0 | 100 | 0.00 |
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 22.383s | 0.000us | 0 | 3 | 0.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 201.030s | 158.152us | 0 | 1 | 0.00 |
| V3 | chip_sw_coremark | chip_sw_coremark | 15.156s | 0.000us | 0 | 1 | 0.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 20.678s | 0.000us | 0 | 3 | 0.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 15.476s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 18.732s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 15.001s | 0.000us | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 13.450s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_jtag_inject_dev | 13.914s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_inject_rma | 13.197s | 0.000us | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 14.547s | 0.000us | 0 | 3 | 0.00 |
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 1288.290s | 905.345us | 0 | 3 | 0.00 | |
| chip_sw_entropy_src_kat_test | 224.090s | 144.304us | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_ast_rng_req | 241.340s | 141.641us | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_0 | 541.500s | 346.747us | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_10 | 488.760s | 302.040us | 3 | 3 | 100.00 | ||
| chip_sw_dma_inline_hashing | 255.920s | 191.501us | 3 | 3 | 100.00 | ||
| chip_sw_dma_abort | 257.000s | 192.920us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 13.895s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 13.827s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 15.206s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 15.252s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 13.255s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 14.579s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 14.717s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 14.307s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 13.201s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 13.024s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_entropy_src_smoketest | 277.450s | 183.060us | 3 | 3 | 100.00 | ||
| chip_sw_mbx_smoketest | 592.080s | 408.194us | 3 | 3 | 100.00 | ||
| TOTAL | 1956 | 2639 | 74.12 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 71.83 | 71.88 | 77.95 | 63.46 | 57.14 | 80.19 | 68.24 | 83.95 |
Job returned non-zero exit code has 399 failures:
0.chip_sw_example_manufacturer.110538801480370879283033409837999783019420002482245127103792858919144605867239
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log
Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 147.266s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_example_manufacturer.21458566214756593379072532438709120527444121345751561169304370360308631770707
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log
Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 24.718s, Critical Path: 0.00s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_data_integrity_escalation.76356976308914455247056196829911290632595687756413798836129456158842390001039
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log
Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 140.714s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_data_integrity_escalation.2707623274037848864232685453812149318685024901577907897647809694462548562604
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log
Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 62.146s, Critical Path: 0.00s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 4 more failures.
0.chip_sw_sleep_pin_wake.14841607811426288194461820213172426853297694423782984060228940033950411290751
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 139.751s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_sleep_pin_wake.15323944509072328855076843820741438921928115390355439144905849060018328937456
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 10.769s, Critical Path: 0.00s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_sleep_pin_retention.38446671594919391672742543542536628710416531823602965876138472988935830453068
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 127.737s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_sleep_pin_retention.5303852630460077875089163195765299495286135325361069326875312889946216528625
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.215s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_uart_tx_rx.21138190255780454614336319452322318365003904436727758111700010783400190473611
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log
Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 119.759s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_uart_tx_rx.34862373498917887275997183129622794821954810952402150126972553672245654924783
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log
Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.126s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 3 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 90 failures:
0.chip_sw_all_escalation_resets.68497921066038666854066262335077571647047395793177528106918243677221729238144
Line 541, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 905.362000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.362000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_all_escalation_resets.21043390541486711052775882284440205958775308726461385970503181098425367481738
Line 536, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 905.474000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.474000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 85 more failures.
0.chip_sw_rstmgr_rst_cnsty_escalation.69856445224189233286760406733433421283061186722506181979480652483051274184404
Line 488, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
UVM_ERROR @ 905.752000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.752000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_rst_cnsty_escalation.83327874271004367032898922732304794312227460530725736792165897793108630312563
Line 487, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
UVM_ERROR @ 905.557000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.557000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 36 failures:
0.chip_sw_otbn_ecdsa_op_irq_jitter_en.80682143152348822621594946528051133682435826339714900775133499722563623691192
Line 467, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_otbn_ecdsa_op_irq_jitter_en.111285906700173382804183430523834425042606227204600405518233659908767329238500
Line 382, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
UVM_FATAL @ 10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_aes_enc_jitter_en.68077092409023294184145587467454902700483079378408925066452233899132548728937
Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aes_enc_jitter_en.98029370120713257606254125720280312285667828366160883392853896062526620864238
Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_hmac_enc_jitter_en.20942250609355491153940759541599531879847611863266232821644930961960504080089
Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_hmac_enc_jitter_en.60070227794809312907173174948582182359712462638848272410592465287590845109757
Line 408, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_dpe_key_derivation_jitter_en.106244733181779366274900533643134449246490682310946217028426726766494673289799
Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
UVM_FATAL @ 10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation_jitter_en.86934692015723730945002307211701611116224458599152085877115698940239934817948
Line 428, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
UVM_FATAL @ 10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_kmac_mode_kmac_jitter_en.64775136598757536318688651113957985257908440503564319985611308339743605030391
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_kmac_mode_kmac_jitter_en.54021596539452109115395291734348563324283397835470988580283604327384280492461
Line 437, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job timed out after * minutes has 32 failures:
0.xbar_access_same_device_slow_rsp.114887794852981243511374950538387566108133288153262946907733677577578432604378
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log
Job timed out after 60 minutes
2.xbar_access_same_device_slow_rsp.102231854136325295453693649327889862660253109461047045081587620364517574924530
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest/run.log
Job timed out after 60 minutes
... and 26 more failures.
46.xbar_stress_all_with_rand_reset.3031431413457100992716529645135806824134204282601927425090675416182229266832
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/46.xbar_stress_all_with_rand_reset/latest/run.log
Job timed out after 60 minutes
52.xbar_stress_all_with_rand_reset.24063995460402766570585853364764004837593380398100196118200858363998694972936
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.xbar_stress_all_with_rand_reset/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
0.chip_sw_spi_device_pass_through.43179411981137208911560402614993506058616260289967374199235155168618620588287
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log
Job timed out after 60 minutes
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 27 failures:
0.chip_tl_errors.72621805502227302258427048516590516292651706974965745419460719941775050391223
Line 229, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
UVM_ERROR @ 118.071000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
UVM_INFO @ 118.071000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_tl_errors.92276381024915729705474524138722675526719188564830386705561109099465715283721
Line 229, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_tl_errors/latest/run.log
Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
UVM_ERROR @ 117.813000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
UVM_INFO @ 117.813000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 18 failures:
0.chip_sw_rstmgr_cpu_info.59292784816737957231873837437887707356840322358019806145045784326732596139792
Line 543, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 375.360000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 375.360000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_cpu_info.44543641251396415892233406825421622916148296390178885332631818313803376658210
Line 509, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 375.104000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 375.104000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_soc_proxy_smoketest.88443216514857363939814564263187696608894972283874782483296888725098605090359
Line 475, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
Offending '((!rstreqs[1]) && (reset_cause != HwReq))'
UVM_ERROR @ 143.424000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 143.424000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_smoketest.95045702907229373109688229086289394262654255949975570311211007926724670183314
Line 408, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest/run.log
Offending '((!rstreqs[1]) && (reset_cause != HwReq))'
UVM_ERROR @ 143.456000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 143.456000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_aes_trans.103954451310387433788775559016036992210569747862922717365667239507512055899553
Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.584000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.584000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_aes_trans.8416358252138214363923416988479747546860667173359302305035816623063112873549
Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.632000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.632000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_hmac_trans.108958885060610224519660319062139264768431481897986363028753894523247266714088
Line 417, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.616000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.616000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_hmac_trans.108276621801595453528849279404877950654825519949242810176532776992308512292846
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_kmac_trans.24738138067661848581846447544212108239736316868896833007897344131631425991342
Line 418, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.680000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_kmac_trans.61121184721710839757596087616365107880630399475690665584187385865040631461570
Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
0.chip_padctrl_attributes.106429417403528224684201771449443039001739025155595361549158535754017076702208
Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
1.chip_padctrl_attributes.67633640635786743982587648702339655571393794808363482055471404996629544872214
Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
0.chip_csr_bit_bash.55212669303051163917197203834320967187763393601956002444508012346362500047298
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_bit_bash.62089790024424320377526705495416349617657785654279812025047780425371059141771
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_csr_aliasing.106166110103179183056964050711455181986900067609861870670758277105791076889206
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_aliasing.92754263793448853975855290883701160350215129376688151969560212476430160664301
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_same_csr_outstanding.69158026369232542584931400462336570340476857481114895768123422720370634630021
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_same_csr_outstanding.113031004309409692127551531632848605238900135803001202777316785216599538249965
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 6 failures:
0.chip_sw_keymgr_dpe_key_derivation.39378451830832121439276094876295430187118186096783907394528048542809022635525
Line 411, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
UVM_ERROR @ 267.579000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11919424803889113231045851227120227085022842666347673562805469126208490810900775021200892342337758828420940535793909341118011362086662628130446661736815708 [0xe394ef50aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd365c25fa17f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 267.579000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation.42654621850335422719083554306702346127492780499542386420379802837305950773614
Line 452, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log
UVM_ERROR @ 267.859000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (9515344364955178448869333446841526092663210244756997340746035979769862020605133609787911914000734684447608724919991455608916046407273852225674608183172188 [0xb5ae08cfaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd333f8b83e7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 267.859000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_dpe_key_derivation_prod.57131241500676821156854072611813011272691101269569396713545310354227653551343
Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
UVM_ERROR @ 267.792000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4010526388610364079556322524227906904791310875512706408112524502819857965862980687669793364771632204411566798764583571692554443002017173504568558778408028 [0x4c930b6daae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3cac5bb9c7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 267.792000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation_prod.24146245418605339596585502337984682249085049169992393380900872280646437605402
Line 455, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
UVM_ERROR @ 267.792000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (3998550078132697753483935619417958873851107590363606943474685773609224633845083087541214152146363407710691935642439765354358399529847224276257599088057436 [0x4c588172aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3ca0e31837f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 267.792000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42093) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:
0.chip_jtag_csr_rw.43573016948888149619968528431340818694260513182414893979342967812785824069880
Line 5959, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 117.016000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42093) { a_addr: 'h30480000 a_data: 'hdf247e0b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3b a_opcode: 'h0 a_user: 'h2697c d_param: 'h0 d_source: 'h3b d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.016000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_jtag_csr_rw.74979609436212281295862831567498901718445704271762634663472669463300573389242
Line 5959, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 117.020000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42093) { a_addr: 'h30480000 a_data: 'h52c98ad1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h1 a_user: 'h248ca d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.020000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_jtag_mem_access.87246836856352567211796451011889941663500279260740328741668366122114963464981
Line 5959, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.016000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42093) { a_addr: 'h30480000 a_data: 'h42ed3848 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h0 a_user: 'h2690f d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.016000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_jtag_mem_access.607407220656792808087157865085829459745878185870006193808955479406063383353
Line 5959, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.021000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42093) { a_addr: 'h30480000 a_data: 'he1c7f678 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc a_opcode: 'h0 a_user: 'h26974 d_param: 'h0 d_source: 'hc d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.021000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 6 failures:
3.chip_sw_all_escalation_resets.76851228831887718548147391703707844398524306994772077588910622747298287421277
Line 452, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 162.200000 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 162.200000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
56.chip_sw_all_escalation_resets.55469488433722761341903585665163379427405778134989500385175104219755928713583
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 162.228000 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 162.228000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 4 failures:
7.chip_sw_all_escalation_resets.111522133505022818985021216255619260575734345880390546615431382961268173975360
Line 411, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest/run.log
UVM_FATAL @ 10.140001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.chip_sw_all_escalation_resets.13716400752135638881984180927196935055321065950607011802054812742811445142569
Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest/run.log
UVM_FATAL @ 10.240001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 3 failures:
0.chip_rv_dm_lc_disabled.26575297130592316657822146370886640920619566968983944818760813131829148104871
Line 230, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 400.023000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x4072c read out mismatch
UVM_INFO @ 400.023000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_rv_dm_lc_disabled.79802533141478400628869780567610172651443537994547119307097273094497619586200
Line 263, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 897.785000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40758 read out mismatch
UVM_INFO @ 897.785000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:
0.chip_sw_example_rom.87864093225988376093910681802515160574839972023086076646415443198318018265651
Line 587, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_example_rom.88843657963551012846131246688895667052769908513439026898355954198569209809848
Line 365, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
0.chip_sw_spi_device_pass_through_collision.75361067954607331957800981785084890478820620155525655817752733640231654464911
Line 454, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_ERROR @ 224.069000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 224.069000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_spi_device_pass_through_collision.70538661797086641574597188894579557702333482382087881647020750420088020992005
Line 534, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_ERROR @ 291.732000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 291.732000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 3 failures:
Test chip_sw_otp_ctrl_escalation has 1 failures.
0.chip_sw_otp_ctrl_escalation.76298973112282699779308139300330914927151152668503736381586622366229306059202
Line 440, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 158.152000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 158.152000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_all_escalation_resets has 2 failures.
95.chip_sw_all_escalation_resets.30270277487619248175467013152958748988267446502394023070595512226766562100116
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 157.972000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 157.972000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
98.chip_sw_all_escalation_resets.113715410532066720737984342298830987538929950892525389378414118904497087134660
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 158.036000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 158.036000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 3 failures:
0.chip_sw_rstmgr_alert_info.111712337059813305761144433780270321395515528072961913011907072846904758840977
Line 529, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
UVM_ERROR @ 289.894000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 289.894000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_alert_info.76313723445429225866577671142933936496233767933065437803527574162230692882231
Line 483, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log
UVM_ERROR @ 290.010000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 290.010000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:
0.chip_sw_soc_proxy_external_wakeup.1395165560907618192446698706224205944615822988062137592898963851178452072882
Line 482, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
UVM_ERROR @ 138.832000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 138.832000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_external_wakeup.62569896445678198391534269618348239593112924878075643090804525652657523884709
Line 443, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log
UVM_ERROR @ 138.776000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 138.776000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns * has 3 failures:
0.chip_sw_soc_proxy_gpios.51234675415573853351752542870297184354299932792226865001032336172494112102903
Line 470, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log
UVM_ERROR @ 136.466000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
UVM_INFO @ 136.466000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_gpios.37640254688714244022594071530775847917155767861754502219474643547870858912974
Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_gpios/latest/run.log
UVM_ERROR @ 136.454000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
UVM_INFO @ 136.454000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 3 failures:
0.chip_sw_aon_timer_irq.87902974679894360312680762145063744928958021436055986998685741773771194114809
Line 493, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
UVM_ERROR @ 575.534000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4355 usec which is not in the range 398 usec and 453 usec
UVM_INFO @ 575.534000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aon_timer_irq.106998814842507370082811990548729409991566838104778385605579218914280627724189
Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log
UVM_ERROR @ 589.558000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4501 usec which is not in the range 411 usec and 468 usec
UVM_INFO @ 589.558000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:
0.chip_sw_aon_timer_wdog_bite_reset.81537864816283920124207347811513360588593934933450338099486707223079971726795
Line 467, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
UVM_ERROR @ 164.339000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 164.339000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aon_timer_wdog_bite_reset.32471736596220910340770421615554201024852739224536540006247147715960362036473
Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
UVM_ERROR @ 164.337000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 164.337000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
0.chip_sw_rv_core_ibex_nmi_irq.88401266400777443187867797316487300326824109407918129842576417149240548901219
Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
UVM_ERROR @ 251.539000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 251.539000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_core_ibex_nmi_irq.76982457377569527975750071721114463298567598097159165779318334422695946594023
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
UVM_ERROR @ 251.578000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 251.578000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
0.chip_sw_kmac_app_rom.20719390094488593253737039964217538973080123329062490178223258972044358890731
Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_kmac_app_rom.18849125846742889348424609144148688656655998303037706834180469270355135178634
Line 427, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * has 3 failures:
0.chip_sw_dma_abort.103652318172795814950116175905483401200284347637674713994759512527446365170711
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
UVM_ERROR @ 192.924000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
UVM_INFO @ 192.924000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_dma_abort.81483215371633061833790006469677034978870929979696288327742109818477975260060
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log
UVM_ERROR @ 192.935000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
UVM_INFO @ 192.935000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32680) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.chip_tl_errors.113229302304160795884494700581056448394928774525551753357909252220977946106789
Line 228, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log
UVM_ERROR @ 118.085000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32680) { a_addr: 'h40714 a_data: 'hbab02cab a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h196c5 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 118.085000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32424) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
25.chip_tl_errors.103169911972886611700971241938189516465449404869356444947837656165220136255921
Line 228, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_tl_errors/latest/run.log
UVM_ERROR @ 117.780000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32424) { a_addr: 'h40738 a_data: 'hbff6458a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h21 a_opcode: 'h4 a_user: 'h19609 d_param: 'h0 d_source: 'h21 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.780000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33950) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
26.chip_tl_errors.33722620388688182286434745469407982616125590661689754079678546743073712545986
Line 228, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.chip_tl_errors/latest/run.log
UVM_ERROR @ 117.819000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33950) { a_addr: 'h4070c a_data: 'h39b57869 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h1a6d3 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.819000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
2.chip_sw_all_escalation_resets.29956705405124312812037752404748649390182222067086359581033841982412704246756
Line 535, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 158.742000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
UVM_INFO @ 158.742000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---