AES/MASKED Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: `da96c41`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	97.173us	2	2	100.00
V1	smoke	aes_smoke	6.000s	113.388us	100	100	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	70.739us	10	10	100.00
V1	csr_rw	aes_csr_rw	3.000s	167.349us	40	40	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	1554.023us	10	10	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	347.927us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	258.105us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	167.349us	40	40	100.00
		aes_csr_aliasing	4.000s	347.927us	10	10	100.00
V1		TOTAL			212	212	100.00
V2	algorithm	aes_smoke	6.000s	113.388us	100	100	100.00
		aes_config_error	14.000s	1956.118us	100	100	100.00
		aes_stress	44.000s	2053.903us	100	100	100.00
V2	key_length	aes_smoke	6.000s	113.388us	100	100	100.00
		aes_config_error	14.000s	1956.118us	100	100	100.00
		aes_stress	44.000s	2053.903us	100	100	100.00
V2	back2back	aes_stress	44.000s	2053.903us	100	100	100.00
		aes_b2b	22.000s	713.155us	100	100	100.00
V2	backpressure	aes_stress	44.000s	2053.903us	100	100	100.00
V2	multi_message	aes_smoke	6.000s	113.388us	100	100	100.00
		aes_config_error	14.000s	1956.118us	100	100	100.00
		aes_stress	44.000s	2053.903us	100	100	100.00
		aes_alert_reset	6.000s	283.751us	100	100	100.00
V2	failure_test	aes_man_cfg_err	10.000s	555.062us	100	100	100.00
		aes_config_error	14.000s	1956.118us	100	100	100.00
		aes_alert_reset	6.000s	283.751us	100	100	100.00
V2	trigger_clear_test	aes_clear	14.000s	1417.553us	100	100	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	567.139us	2	2	100.00
V2	reset_recovery	aes_alert_reset	6.000s	283.751us	100	100	100.00
V2	stress	aes_stress	44.000s	2053.903us	100	100	100.00
V2	sideload	aes_stress	44.000s	2053.903us	100	100	100.00
		aes_sideload	6.000s	218.528us	100	100	100.00
V2	deinitialization	aes_deinit	26.000s	1470.204us	100	100	100.00
V2	stress_all	aes_stress_all	255.000s	49161.088us	20	20	100.00
V2	alert_test	aes_alert_test	3.000s	97.302us	100	100	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	66.150us	40	40	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	66.150us	40	40	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	70.739us	10	10	100.00
		aes_csr_rw	3.000s	167.349us	40	40	100.00
		aes_csr_aliasing	4.000s	347.927us	10	10	100.00
		aes_same_csr_outstanding	3.000s	106.351us	40	40	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	70.739us	10	10	100.00
		aes_csr_rw	3.000s	167.349us	40	40	100.00
		aes_csr_aliasing	4.000s	347.927us	10	10	100.00
		aes_same_csr_outstanding	3.000s	106.351us	40	40	100.00
V2		TOTAL			1002	1002	100.00
V2S	reseeding	aes_reseed	24.000s	2925.602us	100	100	100.00
V2S	fault_inject	aes_fi	10.000s	2911.058us	100	100	100.00
		aes_control_fi	52.000s	10039.708us	570	600	95.00
		aes_cipher_fi	58.000s	10015.182us	663	700	94.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	175.342us	40	40	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	175.342us	40	40	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	175.342us	40	40	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	175.342us	40	40	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	221.845us	40	40	100.00
V2S	tl_intg_err	aes_tl_intg_err	3.000s	317.868us	40	40	100.00
		aes_sec_cm	12.000s	3155.674us	10	10	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	317.868us	40	40	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	283.751us	100	100	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	175.342us	40	40	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	113.388us	100	100	100.00
		aes_stress	44.000s	2053.903us	100	100	100.00
		aes_alert_reset	6.000s	283.751us	100	100	100.00
		aes_core_fi	10.000s	10039.585us	138	140	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	175.342us	40	40	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	108.347us	100	100	100.00
		aes_stress	44.000s	2053.903us	100	100	100.00
V2S	sec_cm_key_sideload	aes_stress	44.000s	2053.903us	100	100	100.00
		aes_sideload	6.000s	218.528us	100	100	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	108.347us	100	100	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	108.347us	100	100	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	108.347us	100	100	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	108.347us	100	100	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	108.347us	100	100	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	44.000s	2053.903us	100	100	100.00
V2S	sec_cm_key_masking	aes_stress	44.000s	2053.903us	100	100	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	2911.058us	100	100	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	2911.058us	100	100	100.00
		aes_control_fi	52.000s	10039.708us	570	600	95.00
		aes_cipher_fi	58.000s	10015.182us	663	700	94.71
		aes_ctr_fi	5.000s	394.514us	100	100	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	2911.058us	100	100	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	2911.058us	100	100	100.00
		aes_control_fi	52.000s	10039.708us	570	600	95.00
		aes_cipher_fi	58.000s	10015.182us	663	700	94.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	58.000s	10015.182us	663	700	94.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	2911.058us	100	100	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	2911.058us	100	100	100.00
		aes_control_fi	52.000s	10039.708us	570	600	95.00
		aes_ctr_fi	5.000s	394.514us	100	100	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	2911.058us	100	100	100.00
		aes_control_fi	52.000s	10039.708us	570	600	95.00
		aes_cipher_fi	58.000s	10015.182us	663	700	94.71
		aes_ctr_fi	5.000s	394.514us	100	100	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	283.751us	100	100	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	2911.058us	100	100	100.00
		aes_control_fi	52.000s	10039.708us	570	600	95.00
		aes_cipher_fi	58.000s	10015.182us	663	700	94.71
		aes_ctr_fi	5.000s	394.514us	100	100	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	2911.058us	100	100	100.00
		aes_control_fi	52.000s	10039.708us	570	600	95.00
		aes_cipher_fi	58.000s	10015.182us	663	700	94.71
		aes_ctr_fi	5.000s	394.514us	100	100	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	2911.058us	100	100	100.00
		aes_control_fi	52.000s	10039.708us	570	600	95.00
		aes_ctr_fi	5.000s	394.514us	100	100	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	2911.058us	100	100	100.00
		aes_control_fi	52.000s	10039.708us	570	600	95.00
		aes_cipher_fi	58.000s	10015.182us	663	700	94.71
V2S		TOTAL			1901	1970	96.50
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	31.000s	2386.731us	0	20	0.00
V3		TOTAL			0	20	0.00
		TOTAL			3115	3204	97.22

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.32	98.60	96.47	99.41	95.35	98.07	97.04	98.51	97.38

Failure Buckets

Job timed out after * minutes has 30 failures:
- Test aes_cipher_fi has 12 failures.
  - 1.aes_cipher_fi.83678970036202161009949618244499714597179914568165086406667333688608178187082
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 58.aes_cipher_fi.83090480570185142203835237621709155749485457791864320656208950816577122024994
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/58.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
- Test aes_control_fi has 18 failures.
  - 4.aes_control_fi.42732482958651015441570338879979642004486430442241665846392393289468172838668
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 35.aes_control_fi.90937983071958041506131806836718799971473118108262824144423221770509959934704
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 16 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 25 failures:
- Test aes_cipher_fi has 25 failures.
  - 12.aes_cipher_fi.24864380426866671851426155353216672845784660563405386899740346720661932829049
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/12.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007173217 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007173217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 55.aes_cipher_fi.71300325626301220159610800849816352354428038747816261329175348053674345143889
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/55.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007490082 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007490082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 23 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 13 failures:

Test aes_stress_all_with_rand_reset has 13 failures.

0.aes_stress_all_with_rand_reset.12972027568771780895598740820784963912952983019894980393253182810426741304990
Line 949, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 564621477 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 564621477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.103797959089357011564573163961205181455415768339387907952567458525787020289201
Line 1180, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3052124053 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3052124053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_control_fi has 12 failures.
  - 25.aes_control_fi.92499998502463425181198580204966833545177241818052753238083102275213821400062
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005907590 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005907590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 86.aes_control_fi.27038819846583902573438600319269700699871657743913680647365652714909869300297
    Line 149, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/86.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003920137 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003920137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 2.aes_stress_all_with_rand_reset.100592506977362986348955313957924121014668896792628196571649938300143666868084
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  51022795 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  51022795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 0.aes_stress_all_with_rand_reset.65743459120191733615315162860227960757394409348817144170917461952635087613474
    Line 166, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  33704185 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  33704185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 6.aes_stress_all_with_rand_reset.69685068968116905881284371703119944091175283350953129433504448446919522138401
    Line 154, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 237653593 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 237653593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.19586008604561208015173448597621678450762275699900822059326121016310268770724
    Line 162, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 650713285 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 650713285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 14.aes_core_fi.74358867723535057370094262076897795975754653773856568083680087206806566074900
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10039584685 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10039584685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 46.aes_core_fi.28389571563297795905950429700813447755751147303966231918749770278447150455063
    Line 134, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/46.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10045146639 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10045146639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.84972986646701156846157709938728078378301212989373512339532861262182312518771
    Line 162, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  25659421 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  25659421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```