CSRNG Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: da96c41

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	198.041us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	138.536us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	213.148us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	10.000s	238.773us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	105.667us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	80.714us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	213.148us	20	20	100.00
		csrng_csr_aliasing	5.000s	105.667us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	16.000s	1339.279us	200	200	100.00
V2	alerts	csrng_alert	47.000s	3221.676us	500	500	100.00
V2	err	csrng_err	4.000s	114.866us	500	500	100.00
V2	cmds	csrng_cmds	605.000s	63558.829us	50	50	100.00
V2	life cycle	csrng_cmds	605.000s	63558.829us	50	50	100.00
V2	stress_all	csrng_stress_all	580.000s	33493.996us	47	50	94.00
V2	intr_test	csrng_intr_test	3.000s	46.467us	50	50	100.00
V2	alert_test	csrng_alert_test	4.000s	172.036us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	19.000s	1533.440us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	19.000s	1533.440us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	138.536us	5	5	100.00
		csrng_csr_rw	4.000s	213.148us	20	20	100.00
		csrng_csr_aliasing	5.000s	105.667us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	153.925us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	138.536us	5	5	100.00
		csrng_csr_rw	4.000s	213.148us	20	20	100.00
		csrng_csr_aliasing	5.000s	105.667us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	153.925us	20	20	100.00
V2		TOTAL			1437	1440	99.79
V2S	tl_intg_err	csrng_sec_cm	5.000s	255.395us	5	5	100.00
		csrng_tl_intg_err	10.000s	275.098us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	3.000s	13.500us	50	50	100.00
		csrng_csr_rw	4.000s	213.148us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	47.000s	3221.676us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	580.000s	33493.996us	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	16.000s	1339.279us	200	200	100.00
		csrng_err	4.000s	114.866us	500	500	100.00
		csrng_sec_cm	5.000s	255.395us	5	5	100.00
V2S	sec_cm_cmd_stage_fsm_sparse	csrng_intr	16.000s	1339.279us	200	200	100.00
		csrng_err	4.000s	114.866us	500	500	100.00
		csrng_sec_cm	5.000s	255.395us	5	5	100.00
V2S	sec_cm_ctr_drbg_fsm_sparse	csrng_intr	16.000s	1339.279us	200	200	100.00
		csrng_err	4.000s	114.866us	500	500	100.00
		csrng_sec_cm	5.000s	255.395us	5	5	100.00
V2S	sec_cm_ctr_drbg_ctr_redun	csrng_intr	16.000s	1339.279us	200	200	100.00
		csrng_err	4.000s	114.866us	500	500	100.00
		csrng_sec_cm	5.000s	255.395us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	16.000s	1339.279us	200	200	100.00
		csrng_err	4.000s	114.866us	500	500	100.00
		csrng_sec_cm	5.000s	255.395us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	47.000s	3221.676us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	16.000s	1339.279us	200	200	100.00
		csrng_err	4.000s	114.866us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	580.000s	33493.996us	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	47.000s	3221.676us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	10.000s	275.098us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	16.000s	1339.279us	200	200	100.00
		csrng_err	4.000s	114.866us	500	500	100.00
		csrng_sec_cm	5.000s	255.395us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	16.000s	1339.279us	200	200	100.00
		csrng_err	4.000s	114.866us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	16.000s	1339.279us	200	200	100.00
		csrng_err	4.000s	114.866us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	16.000s	1339.279us	200	200	100.00
		csrng_err	4.000s	114.866us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	16.000s	1339.279us	200	200	100.00
		csrng_err	4.000s	114.866us	500	500	100.00
		csrng_sec_cm	5.000s	255.395us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	16.000s	1339.279us	200	200	100.00
		csrng_err	4.000s	114.866us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	331.000s	21227.439us	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1627	1630	99.82

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.66	98.72	96.79	99.61	96.80	93.64	95.24	95.85	91.44

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
  • Test csrng_stress_all has 3 failures.

    • 2.csrng_stress_all.103008837847508248747211243262756881965013156067992020759415072504101343981655
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_stress_all/latest/run.log

        UVM_ERROR @ 445895036 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 445895036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.csrng_stress_all.98741141908810233299015949737155623102747907234583363703279072280918661452613
      Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/6.csrng_stress_all/latest/run.log

        UVM_ERROR @ 15935969572 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 15935969572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.