DMA Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: da96c41

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	2147.992us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	1792.120us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	345.789us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	32.385us	5	5	100.00
V1	csr_rw	dma_csr_rw	2.000s	81.200us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	16.000s	1485.141us	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	599.890us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	3.000s	33.034us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	81.200us	20	20	100.00
		dma_csr_aliasing	7.000s	599.890us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	126.000s	14112.425us	5	5	100.00
V2	dma_memory_tl_error	dma_memory_stress	590.000s	217171.090us	3	3	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	1039.000s	96387.051us	3	3	100.00
V2	dma_handshake_stress	dma_handshake_stress	1039.000s	96387.051us	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	590.000s	217171.090us	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	800.000s	302243.979us	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	1039.000s	96387.051us	3	3	100.00
V2	dma_abort	dma_abort	16.000s	2183.910us	5	5	100.00
V2	dma_stress_all	dma_stress_all	202.000s	16576.284us	3	3	100.00
V2	alert_test	dma_alert_test	2.000s	29.444us	50	50	100.00
V2	intr_test	dma_intr_test	2.000s	20.515us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	350.851us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	350.851us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	32.385us	5	5	100.00
		dma_csr_rw	2.000s	81.200us	20	20	100.00
		dma_csr_aliasing	7.000s	599.890us	5	5	100.00
		dma_same_csr_outstanding	3.000s	169.235us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	32.385us	5	5	100.00
		dma_csr_rw	2.000s	81.200us	20	20	100.00
		dma_csr_aliasing	7.000s	599.890us	5	5	100.00
		dma_same_csr_outstanding	3.000s	169.235us	20	20	100.00
V2		TOTAL			164	164	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	23.000s	7425.012us	5	5	100.00
		dma_generic_stress	800.000s	302243.979us	5	5	100.00
		dma_handshake_stress	1039.000s	96387.051us	3	3	100.00
V2S	dma_config_lock	dma_config_lock	11.000s	1682.965us	15	15	100.00
V2S	tl_intg_err	dma_sec_cm	2.000s	13.012us	5	5	100.00
		dma_tl_intg_err	5.000s	904.262us	20	20	100.00
V2S		TOTAL			45	45	100.00
	Unmapped tests	dma_short_transfer	174.000s	14906.990us	25	25	100.00
		dma_longer_transfer	5.000s	176.192us	5	5	100.00
		dma_stress_all_with_rand_reset	9.000s	1727.454us	0	1	0.00
		TOTAL			394	395	99.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.71	97.38	95.83	96.89	96.14	83.12	92.96	95.97	75.85

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.50945265554829306734776987747328117272482629452012935993847106168127773148407
      Line 97, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1727453677ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1727453677ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---