EDN/EDN1 Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: da96c41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.000s	0.000us	0	100	0.00
V1	csr_hw_reset	edn_csr_hw_reset	0.000s	0.000us	0	10	0.00
V1	csr_rw	edn_csr_rw	0.000s	0.000us	0	40	0.00
V1	csr_bit_bash	edn_csr_bit_bash	0.000s	0.000us	0	10	0.00
V1	csr_aliasing	edn_csr_aliasing	0.000s	0.000us	0	10	0.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.000s	0.000us	0	40	0.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.000s	0.000us	0	40	0.00
		edn_csr_aliasing	0.000s	0.000us	0	10	0.00
V1		TOTAL			0	210	0.00
V2	firmware	edn_genbits	0.000s	0.000us	0	600	0.00
V2	csrng_commands	edn_genbits	0.000s	0.000us	0	600	0.00
V2	genbits	edn_genbits	0.000s	0.000us	0	600	0.00
V2	interrupts	edn_intr	0.000s	0.000us	0	100	0.00
V2	alerts	edn_alert	0.000s	0.000us	0	400	0.00
V2	errs	edn_err	0.000s	0.000us	0	200	0.00
V2	disable	edn_disable	0.000s	0.000us	0	100	0.00
		edn_disable_auto_req_mode	0.000s	0.000us	0	100	0.00
V2	stress_all	edn_stress_all	0.000s	0.000us	0	100	0.00
V2	intr_test	edn_intr_test	0.000s	0.000us	0	100	0.00
V2	alert_test	edn_alert_test	0.000s	0.000us	0	100	0.00
V2	tl_d_oob_addr_access	edn_tl_errors	0.000s	0.000us	0	40	0.00
V2	tl_d_illegal_access	edn_tl_errors	0.000s	0.000us	0	40	0.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.000s	0.000us	0	10	0.00
		edn_csr_rw	0.000s	0.000us	0	40	0.00
		edn_csr_aliasing	0.000s	0.000us	0	10	0.00
		edn_same_csr_outstanding	0.000s	0.000us	0	40	0.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.000s	0.000us	0	10	0.00
		edn_csr_rw	0.000s	0.000us	0	40	0.00
		edn_csr_aliasing	0.000s	0.000us	0	10	0.00
		edn_same_csr_outstanding	0.000s	0.000us	0	40	0.00
V2		TOTAL			0	1880	0.00
V2S	tl_intg_err	edn_tl_intg_err	0.000s	0.000us	0	40	0.00
		edn_sec_cm	0.000s	0.000us	0	10	0.00
V2S	sec_cm_config_regwen	edn_regwen	0.000s	0.000us	0	20	0.00
V2S	sec_cm_config_mubi	edn_alert	0.000s	0.000us	0	400	0.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	0.000s	0.000us	0	10	0.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	0.000s	0.000us	0	10	0.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	0.000s	0.000us	0	10	0.00
V2S	sec_cm_ctr_redun	edn_sec_cm	0.000s	0.000us	0	10	0.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.000s	0.000us	0	400	0.00
		edn_sec_cm	0.000s	0.000us	0	10	0.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.000s	0.000us	0	400	0.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	0.000s	0.000us	0	40	0.00
V2S		TOTAL			0	70	0.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	0.000s	0.000us	0	100	0.00
V3		TOTAL			0	100	0.00
		TOTAL			0	2260	0.00

Failure Buckets

• Job killed most likely because its dependent job failed. has 2264 failures:
  • Test edn_tl_errors has 40 failures.

    • 0.edn_tl_errors.103233948226561944217244487333175970193051775593225966974417875458540293541309
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_tl_errors/latest/run.log

    • 1.edn_tl_errors.102076420083393175184474243452385703870232817983625648705543430330883334934781
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_tl_errors/latest/run.log

    • ... and 38 more failures.

  • Test edn_tl_intg_err has 40 failures.

    • 0.edn_tl_intg_err.95003948587991464518550691078138990706447856680867357457473114362403466619468
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_tl_intg_err/latest/run.log

    • 1.edn_tl_intg_err.58594669617579462412684567909762974494957042760719956671719589506136940643536
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_tl_intg_err/latest/run.log

    • ... and 38 more failures.

  • Test edn_intr_test has 100 failures.

    • 0.edn_intr_test.86189057485999064752231131442991151542031483266427503997328397534826966743618
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_intr_test/latest/run.log

    • 1.edn_intr_test.12148223219380855178615255843848743963608336500360719132452498847976343992900
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_intr_test/latest/run.log

    • ... and 98 more failures.

  • Test edn_csr_hw_reset has 10 failures.

    • 0.edn_csr_hw_reset.97948696068682773349694582249650757079504322473817130090021866835363138445190
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_csr_hw_reset/latest/run.log

    • 1.edn_csr_hw_reset.85440956156031669651224919993467631824150802368439746799141403487415303298722
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_csr_hw_reset/latest/run.log

    • ... and 8 more failures.

  • Test edn_csr_rw has 40 failures.

    • 0.edn_csr_rw.36050407394813937932586696279555785537264760006514935754918361989272625530696
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_csr_rw/latest/run.log

    • 1.edn_csr_rw.44552985519555712095565918560082336232596829584612846670624433402075078231587
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_csr_rw/latest/run.log

    • ... and 38 more failures.

  • ... and 17 more tests.
• Job returned non-zero exit code has 4 failures:

  • Test default has 2 failures.

    • default
      Log /nightly/current_run/scratch/master/edn-sim-vcs/default/build.log

            return cls('').absolute()
                   ~~~~~~~~~~~~~~~~^^
          File "/nightly/runs/.local/share/uv/python/cpython-3.13.1-linux-x86_64-gnu/lib/python3.13/pathlib/_local.py", line 649, in absolute
            cwd = os.getcwd()
        FileNotFoundError: [Errno 2] No such file or directory
        ERROR: "/nightly/current_run/.venv/bin/python3 /nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py /nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d/ral_input.yml" exited with an error code. See stderr for details.
        ERROR: Setup failed : Failed to run generator 'ral'
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
        ERROR: Setup failed : Cannot find edn_ral_pkg.sv in /nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
      

    • default
      Log /nightly/current_run/scratch/master/edn-sim-vcs/default/build.log

                                                   ~~~~~~~~^^
          File "/nightly/runs/.local/share/uv/python/cpython-3.13.1-linux-x86_64-gnu/lib/python3.13/pathlib/_abc.py", line 746, in cwd
            return cls('').absolute()
                   ~~~~~~~~~~~~~~~~^^
          File "/nightly/runs/.local/share/uv/python/cpython-3.13.1-linux-x86_64-gnu/lib/python3.13/pathlib/_local.py", line 649, in absolute
            cwd = os.getcwd()
        FileNotFoundError: [Errno 2] No such file or directory
        ERROR: "/nightly/current_run/.venv/bin/python3 /nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py /nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d/ral_input.yml" exited with an error code. See stderr for details.
        ERROR: Setup failed : Failed to run generator 'ral'
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
      

  • Test cover_reg_top has 2 failures.

    • cover_reg_top
      Log /nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/build.log

                                                   ~~~~~~~~^^
          File "/nightly/runs/.local/share/uv/python/cpython-3.13.1-linux-x86_64-gnu/lib/python3.13/pathlib/_abc.py", line 746, in cwd
            return cls('').absolute()
                   ~~~~~~~~~~~~~~~~^^
          File "/nightly/runs/.local/share/uv/python/cpython-3.13.1-linux-x86_64-gnu/lib/python3.13/pathlib/_local.py", line 649, in absolute
            cwd = os.getcwd()
        FileNotFoundError: [Errno 2] No such file or directory
        ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d"
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
      

    • cover_reg_top
      Log /nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/build.log

                                                   ~~~~~~~~^^
          File "/nightly/runs/.local/share/uv/python/cpython-3.13.1-linux-x86_64-gnu/lib/python3.13/pathlib/_abc.py", line 746, in cwd
            return cls('').absolute()
                   ~~~~~~~~~~~~~~~~^^
          File "/nightly/runs/.local/share/uv/python/cpython-3.13.1-linux-x86_64-gnu/lib/python3.13/pathlib/_local.py", line 649, in absolute
            cwd = os.getcwd()
        FileNotFoundError: [Errno 2] No such file or directory
        ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d"
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1