HMAC Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: da96c41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	14.240s	300.452us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.330s	376.793us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.180s	130.971us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	11.290s	14304.101us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.650s	3736.434us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	435.300s	95112.076us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.180s	130.971us	20	20	100.00
		hmac_csr_aliasing	6.650s	3736.434us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	53.490s	37464.798us	10	10	100.00
V2	back_pressure	hmac_back_pressure	107.910s	1851.769us	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	285.610s	26410.371us	30	30	100.00
		hmac_test_sha384_vectors	534.910s	26531.885us	75	75	100.00
		hmac_test_sha512_vectors	530.940s	59139.099us	75	75	100.00
		hmac_test_hmac256_vectors	15.280s	1290.641us	50	50	100.00
		hmac_test_hmac384_vectors	15.470s	700.104us	60	60	100.00
		hmac_test_hmac512_vectors	18.860s	861.652us	75	75	100.00
V2	burst_wr	hmac_burst_wr	34.770s	6041.994us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	1104.720s	6044.180us	10	10	100.00
V2	error	hmac_error	72.020s	1738.447us	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	73.210s	13765.055us	10	10	100.00
V2	save_and_restore	hmac_smoke	14.240s	300.452us	10	10	100.00
		hmac_long_msg	53.490s	37464.798us	10	10	100.00
		hmac_back_pressure	107.910s	1851.769us	25	25	100.00
		hmac_datapath_stress	1104.720s	6044.180us	10	10	100.00
		hmac_burst_wr	34.770s	6041.994us	50	50	100.00
		hmac_stress_all	2758.600s	396455.825us	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	14.240s	300.452us	10	10	100.00
		hmac_long_msg	53.490s	37464.798us	10	10	100.00
		hmac_back_pressure	107.910s	1851.769us	25	25	100.00
		hmac_datapath_stress	1104.720s	6044.180us	10	10	100.00
		hmac_wipe_secret	73.210s	13765.055us	10	10	100.00
		hmac_test_sha256_vectors	285.610s	26410.371us	30	30	100.00
		hmac_test_sha384_vectors	534.910s	26531.885us	75	75	100.00
		hmac_test_sha512_vectors	530.940s	59139.099us	75	75	100.00
		hmac_test_hmac256_vectors	15.280s	1290.641us	50	50	100.00
		hmac_test_hmac384_vectors	15.470s	700.104us	60	60	100.00
		hmac_test_hmac512_vectors	18.860s	861.652us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	14.240s	300.452us	10	10	100.00
		hmac_long_msg	53.490s	37464.798us	10	10	100.00
		hmac_back_pressure	107.910s	1851.769us	25	25	100.00
		hmac_datapath_stress	1104.720s	6044.180us	10	10	100.00
		hmac_burst_wr	34.770s	6041.994us	50	50	100.00
		hmac_error	72.020s	1738.447us	10	10	100.00
		hmac_wipe_secret	73.210s	13765.055us	10	10	100.00
		hmac_test_sha256_vectors	285.610s	26410.371us	30	30	100.00
		hmac_test_sha384_vectors	534.910s	26531.885us	75	75	100.00
		hmac_test_sha512_vectors	530.940s	59139.099us	75	75	100.00
		hmac_test_hmac256_vectors	15.280s	1290.641us	50	50	100.00
		hmac_test_hmac384_vectors	15.470s	700.104us	60	60	100.00
		hmac_test_hmac512_vectors	18.860s	861.652us	75	75	100.00
		hmac_stress_all	2758.600s	396455.825us	50	50	100.00
V2	stress_all	hmac_stress_all	2758.600s	396455.825us	50	50	100.00
V2	alert_test	hmac_alert_test	0.930s	19.035us	50	50	100.00
V2	intr_test	hmac_intr_test	0.880s	47.388us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.090s	1138.010us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.090s	1138.010us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.330s	376.793us	5	5	100.00
		hmac_csr_rw	1.180s	130.971us	20	20	100.00
		hmac_csr_aliasing	6.650s	3736.434us	5	5	100.00
		hmac_same_csr_outstanding	2.060s	130.108us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.330s	376.793us	5	5	100.00
		hmac_csr_rw	1.180s	130.971us	20	20	100.00
		hmac_csr_aliasing	6.650s	3736.434us	5	5	100.00
		hmac_same_csr_outstanding	2.060s	130.108us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_tl_intg_err	3.810s	234.303us	20	20	100.00
		hmac_sec_cm	1.340s	63.361us	5	5	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	3.810s	234.303us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	14.240s	300.452us	10	10	100.00
V3	stress_reset	hmac_stress_reset	7.730s	144.390us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	574.040s	5617.399us	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	3.150s	178.740us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.06	99.79	96.80	100.00	100.00	99.67	97.14	100.00