KEYMGR Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: `da96c41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	33.270s	6251.874us	50	50	100.00
V1	random	keymgr_random	24.580s	2302.156us	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.720s	263.130us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.930s	284.290us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.540s	3575.287us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	11.190s	5154.198us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.540s	138.521us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.930s	284.290us	20	20	100.00
		keymgr_csr_aliasing	11.190s	5154.198us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	71.900s	1906.858us	49	50	98.00
V2	sideload	keymgr_sideload	37.720s	2989.178us	50	50	100.00
		keymgr_sideload_kmac	42.820s	6419.509us	50	50	100.00
		keymgr_sideload_aes	28.090s	10074.535us	50	50	100.00
		keymgr_sideload_otbn	34.030s	1459.266us	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	18.890s	3209.263us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	21.190s	2127.894us	47	50	94.00
V2	kmac_error_response	keymgr_kmac_rsp_err	15.290s	2280.379us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	56.320s	14576.891us	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	57.940s	4818.375us	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	16.940s	4305.034us	50	50	100.00
V2	stress_all	keymgr_stress_all	363.760s	28408.819us	49	50	98.00
V2	intr_test	keymgr_intr_test	1.110s	12.870us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.210s	84.342us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.210s	152.566us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.210s	152.566us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.720s	263.130us	5	5	100.00
		keymgr_csr_rw	1.930s	284.290us	20	20	100.00
		keymgr_csr_aliasing	11.190s	5154.198us	5	5	100.00
		keymgr_same_csr_outstanding	3.740s	441.864us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.720s	263.130us	5	5	100.00
		keymgr_csr_rw	1.930s	284.290us	20	20	100.00
		keymgr_csr_aliasing	11.190s	5154.198us	5	5	100.00
		keymgr_same_csr_outstanding	3.740s	441.864us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	19.700s	1569.065us	5	5	100.00
V2S	tl_intg_err	keymgr_tl_intg_err	7.820s	1121.574us	20	20	100.00
		keymgr_sec_cm	19.700s	1569.065us	5	5	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.320s	307.334us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.320s	307.334us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.320s	307.334us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.320s	307.334us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.380s	2774.646us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	19.700s	1569.065us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	19.700s	1569.065us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.820s	1121.574us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.320s	307.334us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	71.900s	1906.858us	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_csr_rw	1.930s	284.290us	20	20	100.00
		keymgr_random	24.580s	2302.156us	50	50	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_csr_rw	1.930s	284.290us	20	20	100.00
		keymgr_random	24.580s	2302.156us	50	50	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_csr_rw	1.930s	284.290us	20	20	100.00
		keymgr_random	24.580s	2302.156us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	21.190s	2127.894us	47	50	94.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	57.940s	4818.375us	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	57.940s	4818.375us	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	24.580s	2302.156us	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	12.070s	1359.187us	49	50	98.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	19.700s	1569.065us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	19.700s	1569.065us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	19.700s	1569.065us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	32.540s	1793.445us	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	21.190s	2127.894us	47	50	94.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	19.700s	1569.065us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	19.700s	1569.065us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	19.700s	1569.065us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	32.540s	1793.445us	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	32.540s	1793.445us	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	19.700s	1569.065us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	32.540s	1793.445us	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	19.700s	1569.065us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	32.540s	1793.445us	49	50	98.00
V2S		TOTAL			163	165	98.79
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	16.360s	2421.461us	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1077	1110	97.03

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.65	99.13	98.15	98.33	100.00	99.01	97.72	91.18

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test keymgr_stress_all_with_rand_reset has 23 failures.
  - 1.keymgr_stress_all_with_rand_reset.92721517514082532714064075892763668650160615699824738649999182342438623318716
    Line 174, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 222009403 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 222009403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.keymgr_stress_all_with_rand_reset.101766144474710233624063315431918599060692439707169336315240260374795876496387
    Line 94, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 121519703 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 121519703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 21 more failures.
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_lc_disable has 1 failures.
  - 2.keymgr_lc_disable.25580682238167493823007508375190374992510826786424283833787608658131145713794
    Line 127, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  19193515 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  19193515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_cfg_regwen has 1 failures.
  - 19.keymgr_cfg_regwen.20635425826443491083521186679885506614138645293778197676938309484719832686159
    Line 735, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @ 144185466 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 144185466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sideload_protect has 1 failures.
  - 25.keymgr_sideload_protect.55320691054378216453434601803346023832084855726293893134846485508814115806181
    Line 156, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/25.keymgr_sideload_protect/latest/run.log
```
  UVM_ERROR @  30460320 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  30460320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1142) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test keymgr_stress_all_with_rand_reset has 2 failures.
  - 29.keymgr_stress_all_with_rand_reset.94951891458266780396703228498895801052886132727544837121074319964526046194659
    Line 241, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1713013132 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1713013132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 44.keymgr_stress_all_with_rand_reset.41811091324038448265287688330708971586955715150329479019179114684183040324436
    Line 994, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 657870578 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 657870578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Attestation Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

1.keymgr_lc_disable.30194787450748437168327805540174988400668142157283638432804746143532821139541
Line 325, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  51039303 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (4736054369614650758125098444119400864198459994546007710127009450754386850674332291907213213259047727066422639496979023470095182075659239384609605623799583 [0x5a6d59fe9a9089d42e2ca187eee1c904baab8624a6b7dc3844cfc2609370742954b7323049f797a0077ff455cbdaccfe55bfca76956c7182bf2027a03fa4df1f] vs 4736054369614650758125098444119400864198459994546007710127009450754386850674332291907213213259047727066422639496979023470095182075659239384609605623799583 [0x5a6d59fe9a9089d42e2ca187eee1c904baab8624a6b7dc3844cfc2609370742954b7323049f797a0077ff455cbdaccfe55bfca76956c7182bf2027a03fa4df1f]) KMAC key at state StDisabled for Attestation Kmac
  UVM_INFO @  51039303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Attestation Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

7.keymgr_stress_all.37713649120959077869709999476752219646918000904902737165943675417638181915635
Line 2207, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 360334576 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (9721547969871571575213849286759036758168733858482263419831588903556588573084519192073186632679194797949557091779978575766253631902366080581043788156978340 [0xb99defc7eb2ba5a34dac582df4f2bca96f945da672c07e0febc053ed017a83fe45210103ea9b1b7bd4d39d4cd9e0baef0b25a8630e22ba0d3e5ae30a260b44a4] vs 9721547969871571575213849286759036758168733858482263419831588903556588573084519192073186632679194797949557091779978575766253631902366080581043788156978340 [0xb99defc7eb2ba5a34dac582df4f2bca96f945da672c07e0febc053ed017a83fe45210103ea9b1b7bd4d39d4cd9e0baef0b25a8630e22ba0d3e5ae30a260b44a4]) AES key at state StOwnerIntKey for Attestation Aes
  UVM_INFO @ 360334576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 21.keymgr_stress_all_with_rand_reset.30908943202396453907735424996821434923422141348746456024249347797390079749711
    Line 611, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 436554201 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 436554201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

25.keymgr_lc_disable.32258922927777960548658190407074177349748422214565138369923866918375366704915
Line 240, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/25.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 1005662205 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (883068585948881301480571180068463059119550385834745332844832230150513550596893538766436193041841331093575143841507395209705955559213134272841101038678420 [0x10dc596e0cec431ac6e7f360dae46fb29e567a03c13878c4744a869dea67711065139bbc59e72d6e7be394b52806e602f2ee6e243f9a5f256b020fc14c017194] vs 883068585948881301480571180068463059119550385834745332844832230150513550596893538766436193041841331093575143841507395209705955559213134272841101038678420 [0x10dc596e0cec431ac6e7f360dae46fb29e567a03c13878c4744a869dea67711065139bbc59e72d6e7be394b52806e602f2ee6e243f9a5f256b020fc14c017194]) AES key at state StCreatorRootKey for Attestation Aes
  UVM_INFO @ 1005662205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (keymgr_if.sv:380) [keymgr_if] timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 43.keymgr_custom_cm.22556256357677986764523191736278122069428794376378390750050407545144686123013
    Line 107, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/43.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @  93729899 ps: (keymgr_if.sv:380) [keymgr_if] timeout occurred!
  UVM_INFO @  93729899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```