KEYMGR_DPE Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: da96c41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	244.070s	17497.178us	48	50	96.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.470s	72.704us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.260s	121.486us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	7.370s	388.421us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	7.840s	290.886us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	2.080s	57.192us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.260s	121.486us	20	20	100.00
		keymgr_dpe_csr_aliasing	7.840s	290.886us	5	5	100.00
V1		TOTAL			103	105	98.10
V2	intr_test	keymgr_dpe_intr_test	1.170s	180.154us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.430s	19.994us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	3.370s	595.477us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	3.370s	595.477us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.470s	72.704us	5	5	100.00
		keymgr_dpe_csr_rw	1.260s	121.486us	20	20	100.00
		keymgr_dpe_csr_aliasing	7.840s	290.886us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.930s	77.089us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.470s	72.704us	5	5	100.00
		keymgr_dpe_csr_rw	1.260s	121.486us	20	20	100.00
		keymgr_dpe_csr_aliasing	7.840s	290.886us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.930s	77.089us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	9.750s	1419.408us	5	5	100.00
		keymgr_dpe_tl_intg_err	6.130s	1088.492us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	2.780s	200.732us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	2.780s	200.732us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	2.780s	200.732us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	2.780s	200.732us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	6.300s	754.961us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	9.750s	1419.408us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	9.750s	1419.408us	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			308	310	99.35

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.59	97.62	90.22	63.15	75.68	94.61	97.64	17.22

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
  • Test keymgr_dpe_smoke has 2 failures.

    • 13.keymgr_dpe_smoke.19263806936046649537720143539689986634417089954451314533943216229297310864696
      Line 4436, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/13.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @ 11812605744 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 11812605744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 18.keymgr_dpe_smoke.61390698250214017837998454493379000370683223915299886350644003098547003956070
      Line 3853, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/18.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @ 27647976632 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 27647976632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---