KMAC/MASKED Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: `da96c41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	93.460s	20657.716us	99	100	99.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.450s	66.312us	10	10	100.00
V1	csr_rw	kmac_csr_rw	1.580s	31.931us	40	40	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.380s	4223.465us	10	10	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.350s	2164.206us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.880s	92.670us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.580s	31.931us	40	40	100.00
		kmac_csr_aliasing	7.350s	2164.206us	10	10	100.00
V1	mem_walk	kmac_mem_walk	0.990s	13.943us	10	10	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.520s	160.332us	10	10	100.00
V1		TOTAL			229	230	99.57
V2	long_msg_and_output	kmac_long_msg_and_output	3734.020s	236516.137us	100	100	100.00
V2	burst_write	kmac_burst_write	1498.780s	55279.123us	100	100	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	2430.900s	319634.490us	10	10	100.00
		kmac_test_vectors_sha3_256	2138.080s	372870.685us	10	10	100.00
		kmac_test_vectors_sha3_384	1210.060s	55900.336us	10	10	100.00
		kmac_test_vectors_sha3_512	1123.570s	34197.262us	10	10	100.00
		kmac_test_vectors_shake_128	202.930s	25853.355us	10	10	100.00
		kmac_test_vectors_shake_256	1819.460s	61405.681us	10	10	100.00
		kmac_test_vectors_kmac	3.720s	103.790us	10	10	100.00
		kmac_test_vectors_kmac_xof	3.300s	52.850us	10	10	100.00
V2	sideload	kmac_sideload	486.490s	44222.539us	100	100	100.00
V2	app	kmac_app	330.320s	72934.000us	100	100	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	370.410s	13855.634us	20	20	100.00
V2	entropy_refresh	kmac_entropy_refresh	362.500s	22068.126us	100	100	100.00
V2	error	kmac_error	410.830s	27764.222us	100	100	100.00
V2	key_error	kmac_key_error	26.340s	26285.683us	100	100	100.00
V2	sideload_invalid	kmac_sideload_invalid	127.420s	10033.873us	92	100	92.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.650s	2280.770us	40	40	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.840s	5052.552us	40	40	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	76.250s	96089.765us	20	20	100.00
V2	lc_escalation	kmac_lc_escalation	38.900s	899.658us	100	100	100.00
V2	stress_all	kmac_stress_all	2793.130s	37675.597us	99	100	99.00
V2	intr_test	kmac_intr_test	1.110s	47.223us	100	100	100.00
V2	alert_test	kmac_alert_test	1.250s	134.638us	100	100	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.300s	899.938us	40	40	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.300s	899.938us	40	40	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.450s	66.312us	10	10	100.00
		kmac_csr_rw	1.580s	31.931us	40	40	100.00
		kmac_csr_aliasing	7.350s	2164.206us	10	10	100.00
		kmac_same_csr_outstanding	2.730s	115.015us	40	40	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.450s	66.312us	10	10	100.00
		kmac_csr_rw	1.580s	31.931us	40	40	100.00
		kmac_csr_aliasing	7.350s	2164.206us	10	10	100.00
		kmac_same_csr_outstanding	2.730s	115.015us	40	40	100.00
V2		TOTAL			1471	1480	99.39
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.280s	124.262us	40	40	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.280s	124.262us	40	40	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.280s	124.262us	40	40	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.280s	124.262us	40	40	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.720s	353.102us	39	40	97.50
V2S	tl_intg_err	kmac_tl_intg_err	4.280s	366.910us	40	40	100.00
		kmac_sec_cm	107.550s	7621.801us	10	10	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.280s	366.910us	40	40	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	38.900s	899.658us	100	100	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	93.460s	20657.716us	99	100	99.00
V2S	sec_cm_key_sideload	kmac_sideload	486.490s	44222.539us	100	100	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.280s	124.262us	40	40	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	107.550s	7621.801us	10	10	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	107.550s	7621.801us	10	10	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	107.550s	7621.801us	10	10	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	93.460s	20657.716us	99	100	99.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	38.900s	899.658us	100	100	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	107.550s	7621.801us	10	10	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	342.490s	7848.030us	20	20	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	93.460s	20657.716us	99	100	99.00
V2S		TOTAL			149	150	99.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	221.290s	5076.041us	15	20	75.00
V3		TOTAL			15	20	75.00
		TOTAL			1864	1880	99.15

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.13	99.20	94.49	99.89	79.58	97.08	97.83	97.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 1.kmac_stress_all_with_rand_reset.21119493981462139430265372699349122379457618157623412412208775923255785387829
    Line 174, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2173046654 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2173046654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.44891567263548138127113140731099103441154011538957749621656347558532790668816
    Line 359, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13823777001 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13823777001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:

Test kmac_smoke has 1 failures.

10.kmac_smoke.80535259726713229336827398504076265798796450421726876084866740118620320038235
Line 74, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_smoke/latest/run.log

  UVM_ERROR @  94485335 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  94485335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

30.kmac_stress_all.25680055090284592245342894746184424845071021045063678916461933257248973099788
Line 206, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/30.kmac_stress_all/latest/run.log

  UVM_ERROR @ 15728197070 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 15728197070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 8.kmac_sideload_invalid.34112811129921284487651324680726768787450670815090723255155387871914326228702
    Line 77, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10034588254 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xed63e000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10034588254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 41.kmac_sideload_invalid.59224332808614992211145676225536182259344666846472734720458814277030664653135
    Line 77, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/41.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10131603288 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf9669000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10131603288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 8.kmac_stress_all_with_rand_reset.17936729611314742347993643504128952013696910444544439341020553659764768803541
    Line 198, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1429323110 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 1429323110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.kmac_stress_all_with_rand_reset.37903208062217758612399267079109122197132406927083375251387508445587227802114
    Line 428, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8322817490 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 8322817490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 16.kmac_sideload_invalid.110229861711236429851026617634014699671259565819060919198313456439704586867021
    Line 80, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10033872614 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa00ea000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10033872614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 48.kmac_sideload_invalid.107780018431660595671028400861763120007458278217708229430804614416765033541676
    Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/48.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10056889936 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x21292000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10056889936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 9.kmac_shadow_reg_errors_with_csr_rw.14083061084768818453316219540604432947346078991940899852257950335415189517957
    Line 285, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 286590814 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (577288968 [0x2268bb08] vs 1064480566 [0x3f72af36]) Regname: kmac_reg_block.prefix_5 reset value: 0x0
  UVM_INFO @ 286590814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 0.kmac_sideload_invalid.32830390605179394011450990474207374868935802780493666208772747676390348321135
    Line 86, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10068375371 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x48f1e000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10068375371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 10.kmac_sideload_invalid.17285467707664302063056173070189204641109212468312442522432932570637409050773
    Line 83, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10219131503 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xeabda000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10219131503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 13.kmac_sideload_invalid.24842390645638169746378537662394611778381439480873114046010358428671984091907
    Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/13.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10092213153 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa36b3000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10092213153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 26.kmac_sideload_invalid.9756814561885988034080268924754707089160079908255052084776077970518828366304
    Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/26.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10068082728 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9d020000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10068082728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```