MBX Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: da96c41

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 mbx_smoke mbx_smoke 97.000s 26365.131us 2 2 100.00
V1 csr_hw_reset mbx_csr_hw_reset 2.000s 23.863us 5 5 100.00
V1 csr_rw mbx_csr_rw 2.000s 38.159us 20 20 100.00
V1 csr_bit_bash mbx_csr_bit_bash 6.000s 519.544us 5 5 100.00
V1 csr_aliasing mbx_csr_aliasing 2.000s 153.322us 5 5 100.00
V1 csr_mem_rw_with_rand_reset mbx_csr_mem_rw_with_rand_reset 3.000s 164.263us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr mbx_csr_rw 2.000s 38.159us 20 20 100.00
mbx_csr_aliasing 2.000s 153.322us 5 5 100.00
V1 TOTAL 57 57 100.00
V2 mbx_stress mbx_stress 178.000s 9144.483us 2 2 100.00
V2 mbx_max_activity mbx_stress_zero_delays 33.000s 294.468us 0 2 0.00
V2 mbx_imbx_oob mbx_imbx_oob 40.000s 3144.892us 0 2 0.00
V2 mbx_doe_intr_msg mbx_doe_intr_msg 50.000s 1838.805us 5 5 100.00
V2 alert_test mbx_alert_test 2.000s 21.340us 50 50 100.00
V2 intr_test mbx_intr_test 2.000s 13.810us 50 50 100.00
V2 tl_d_oob_addr_access mbx_tl_errors 6.000s 586.728us 20 20 100.00
V2 tl_d_illegal_access mbx_tl_errors 6.000s 586.728us 20 20 100.00
V2 tl_d_outstanding_access mbx_csr_hw_reset 2.000s 23.863us 5 5 100.00
mbx_csr_rw 2.000s 38.159us 20 20 100.00
mbx_csr_aliasing 2.000s 153.322us 5 5 100.00
mbx_same_csr_outstanding 3.000s 260.937us 20 20 100.00
V2 tl_d_partial_access mbx_csr_hw_reset 2.000s 23.863us 5 5 100.00
mbx_csr_rw 2.000s 38.159us 20 20 100.00
mbx_csr_aliasing 2.000s 153.322us 5 5 100.00
mbx_same_csr_outstanding 3.000s 260.937us 20 20 100.00
V2 TOTAL 147 151 97.35
V2S tl_intg_err mbx_sec_cm 2.000s 33.204us 5 5 100.00
mbx_tl_intg_err 6.000s 992.898us 20 20 100.00
V2S TOTAL 25 25 100.00
TOTAL 229 233 98.28

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
92.93 95.53 88.83 95.98 90.99 86.12 -- 97.01 85.35

Failure Buckets