OTBN Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: `da96c41`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	73.885us	1	1	100.00
V1	single_binary	otbn_single	38.000s	876.308us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	25.354us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	29.838us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	6.000s	255.427us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	4.000s	23.109us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	36.071us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	29.838us	20	20	100.00
		otbn_csr_aliasing	4.000s	23.109us	5	5	100.00
V1	mem_walk	otbn_mem_walk	47.000s	7116.448us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	15.000s	1953.666us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	34.000s	100.231us	10	10	100.00
V2	multi_error	otbn_multi_err	59.000s	1612.562us	1	1	100.00
V2	back_to_back	otbn_multi	2197.000s	6671.780us	10	10	100.00
V2	stress_all	otbn_stress_all	212.000s	891.429us	10	10	100.00
V2	lc_escalation	otbn_escalate	23.000s	204.315us	58	60	96.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	31.036us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	26.000s	159.725us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	28.253us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	34.717us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	9.000s	51.328us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	9.000s	51.328us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	25.354us	5	5	100.00
		otbn_csr_rw	6.000s	29.838us	20	20	100.00
		otbn_csr_aliasing	4.000s	23.109us	5	5	100.00
		otbn_same_csr_outstanding	5.000s	31.489us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	25.354us	5	5	100.00
		otbn_csr_rw	6.000s	29.838us	20	20	100.00
		otbn_csr_aliasing	4.000s	23.109us	5	5	100.00
		otbn_same_csr_outstanding	5.000s	31.489us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	12.000s	75.903us	10	10	100.00
		otbn_dmem_err	16.000s	54.319us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	59.834us	5	5	100.00
		otbn_controller_ispr_rdata_err	28.000s	95.290us	5	5	100.00
		otbn_mac_bignum_acc_err	24.000s	245.703us	5	5	100.00
		otbn_urnd_err	5.000s	24.733us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	18.210us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	20.717us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	53.664us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
		otbn_tl_intg_err	22.000s	140.175us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	38.000s	218.610us	17	20	85.00
V2S	prim_fsm_check	otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	73.885us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	54.319us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	75.903us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	22.000s	140.175us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	23.000s	204.315us	58	60	96.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	75.903us	10	10	100.00
		otbn_dmem_err	16.000s	54.319us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	31.036us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	18.210us	5	5	100.00
		otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	38.000s	876.308us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	75.903us	10	10	100.00
		otbn_dmem_err	16.000s	54.319us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	31.036us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	18.210us	5	5	100.00
		otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	23.000s	204.315us	58	60	96.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	75.903us	10	10	100.00
		otbn_dmem_err	16.000s	54.319us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	31.036us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	18.210us	5	5	100.00
		otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	38.000s	876.308us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	27.833us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	74.884us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	80.000s	194.257us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	80.000s	194.257us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	15.000s	51.070us	8	10	80.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	22.000s	114.281us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	108.899us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	108.899us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	331.706us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	38.000s	876.308us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	38.000s	876.308us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	38.000s	876.308us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2197.000s	6671.780us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	38.000s	876.308us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	38.000s	876.308us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	20.000s	66.254us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	38.000s	876.308us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1916.000s	8323.622us	2	5	40.00
V2S		TOTAL			151	163	92.64
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	426.000s	26673.047us	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			564	585	96.41

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.04	99.60	95.37	99.69	93.33	93.33	100.00	97.06	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test otbn_stress_all_with_rand_reset has 5 failures.
  - 0.otbn_stress_all_with_rand_reset.38589401425041983869900499078584685058024632046011031473096740640717347953624
    Line 249, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 783975667 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 783975667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.otbn_stress_all_with_rand_reset.16550945922369501761647179177314189134795512468727155845288698675422456229018
    Line 534, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11652538237 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11652538237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_sec_wipe_err has 3 failures.

2.otbn_sec_wipe_err.77546203601153225732270412743969409139359970484416757030826117994318843296369
Line 110, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 331705713 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 331705713 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 331705713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_sec_wipe_err.2325672848813095392093092456452542064268009826130503649267651923388744245379
Line 112, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/5.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22175956 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  22175956 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  22175956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test otbn_escalate has 2 failures.

12.otbn_escalate.30152973043709633567576099449934924307207285255495977936552585674376203565132
Line 116, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/12.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17116477 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  17116477 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  17116477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.otbn_escalate.89262272668587761474998649722826208224687177345921900360429378141724251793781
Line 121, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/44.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 9860790 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   9860790 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   9860790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.88583548835817831207531705577382134771787950404980187390686120841017326730540
Line 102, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 111336193 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 111336193 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 111336193 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 111336193 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 111336193 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

2.otbn_sec_cm.59643182081432404713455858009359615640354979356216439629691758703832796114988
Line 84, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 6054003 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 6054003 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 6054003 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 6054003 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 6054003 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
- Test otbn_passthru_mem_tl_intg_err has 2 failures.
  - 1.otbn_passthru_mem_tl_intg_err.40901397004682222560272367317578512147617187822720909366070997508780719343992
    Line 83, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   1463445 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   1463445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.otbn_passthru_mem_tl_intg_err.14480730010812313499229158132275361322374226769839141003346661002323084942962
    Line 83, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/6.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  12708969 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  12708969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:129) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 0.otbn_rf_base_intg_err.52531060523006107204453274913292599379283681040032122385977963620546493120952
    Line 112, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  51069624 ps: (otbn_rf_base_intg_err_vseq.sv:129) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
  UVM_INFO @  51069624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 1.otbn_rf_base_intg_err.70427654151615144334018708582331099244086072852195085637732711587037611848648
    Line 112, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_rf_base_intg_err/latest/run.log
```
  UVM_ERROR @  37246632 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  37246632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.4249893385675385440246865622185707062674207258801366773344678840763384442761
    Line 168, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  35031398 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  35031398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.20376675892074686562475941895940703534383061481772418588962918518049651331901
    Line 275, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1168201822 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1168201822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,969): Assertion OnlyWriteLoadDataBignumWhenDMemValid_A has failed has 1 failures:

Test otbn_ctrl_redun has 1 failures.

8.otbn_ctrl_redun.88215716578794900377456966962892803543509096008806684532964595756659688020532
Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,969): (time 28240028 PS) Assertion tb.dut.u_otbn_core.OnlyWriteLoadDataBignumWhenDMemValid_A has failed
  UVM_ERROR @  28240028 ps: (otbn_core.sv:969) [ASSERT FAILED] OnlyWriteLoadDataBignumWhenDMemValid_A
  UVM_INFO @  28240028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 11.otbn_passthru_mem_tl_intg_err.588478565059651051706188654868267486227395007032584204507286745802648507823
    Line 83, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/11.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  22419045 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  22419045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```