ROM_CTRL/32KB Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: da96c41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	14.090s	314.762us	4	4	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.500s	353.841us	10	10	100.00
V1	csr_rw	rom_ctrl_csr_rw	17.530s	1032.554us	40	40	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.690s	298.914us	10	10	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.520s	288.055us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.160s	1063.098us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	17.530s	1032.554us	40	40	100.00
		rom_ctrl_csr_aliasing	10.520s	288.055us	10	10	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.500s	296.480us	10	10	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.810s	299.763us	10	10	100.00
V1		TOTAL			134	134	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	9.490s	387.006us	4	4	100.00
V2	stress_all	rom_ctrl_stress_all	51.990s	802.223us	40	40	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	23.250s	3837.607us	4	4	100.00
V2	alert_test	rom_ctrl_alert_test	15.610s	19611.756us	100	100	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.040s	9019.293us	40	40	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.040s	9019.293us	40	40	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.500s	353.841us	10	10	100.00
		rom_ctrl_csr_rw	17.530s	1032.554us	40	40	100.00
		rom_ctrl_csr_aliasing	10.520s	288.055us	10	10	100.00
		rom_ctrl_same_csr_outstanding	14.980s	215.540us	40	40	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.500s	353.841us	10	10	100.00
		rom_ctrl_csr_rw	17.530s	1032.554us	40	40	100.00
		rom_ctrl_csr_aliasing	10.520s	288.055us	10	10	100.00
		rom_ctrl_same_csr_outstanding	14.980s	215.540us	40	40	100.00
V2		TOTAL			228	228	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	300.270s	21719.808us	36	40	90.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	70.290s	1571.683us	40	40	100.00
V2S	tl_intg_err	rom_ctrl_tl_intg_err	158.050s	634.563us	40	40	100.00
		rom_ctrl_sec_cm	534.390s	841.360us	3	10	30.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	534.390s	841.360us	3	10	30.00
V2S	prim_count_check	rom_ctrl_sec_cm	534.390s	841.360us	3	10	30.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	300.270s	21719.808us	36	40	90.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	300.270s	21719.808us	36	40	90.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	300.270s	21719.808us	36	40	90.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	300.270s	21719.808us	36	40	90.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	300.270s	21719.808us	36	40	90.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	534.390s	841.360us	3	10	30.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	534.390s	841.360us	3	10	30.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	14.090s	314.762us	4	4	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	14.090s	314.762us	4	4	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	14.090s	314.762us	4	4	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	158.050s	634.563us	40	40	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	300.270s	21719.808us	36	40	90.00
		rom_ctrl_kmac_err_chk	23.250s	3837.607us	4	4	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	300.270s	21719.808us	36	40	90.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	300.270s	21719.808us	36	40	90.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	300.270s	21719.808us	36	40	90.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	70.290s	1571.683us	40	40	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	534.390s	841.360us	3	10	30.00
V2S		TOTAL			119	130	91.54
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	500.980s	40702.225us	40	40	100.00
V3		TOTAL			40	40	100.00
		TOTAL			521	532	97.93

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.46	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 5 failures:

  • Test rom_ctrl_sec_cm has 5 failures.

    • 0.rom_ctrl_sec_cm.114988846956544392233092427066720808139192900832165822558480303356654465638672
      Line 167, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 12273742ps failed at 12273742ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 12273742ps failed at 12273742ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 1.rom_ctrl_sec_cm.102722543222168112366072785941602502931953690499074263096863948024548499508440
      Line 188, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 174127781ps failed at 174127781ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 174127781ps failed at 174127781ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • ... and 3 more failures.

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 4 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 4 failures.

    • 2.rom_ctrl_corrupt_sig_fatal_chk.26418244435956266839902810377396214059017380922181788786902105399792717691906
      Line 77, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 202455881 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 202455881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.rom_ctrl_corrupt_sig_fatal_chk.57893445245776953961359151281028199666493338603371198554507780466525454176979
      Line 83, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1137311021 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1137311021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 2.rom_ctrl_sec_cm.15746644789567082701661575345123046036120162931981364267128319494770993303716
      Line 244, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 63144093ps failed at 63144093ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 63185760ps failed at 63185760ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 2.rom_ctrl_sec_cm.38100735828194306792226418344452294780578628374814476239281456834463287241738
      Line 223, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 8188706ps failed at 8188706ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 8188706ps failed at 8188706ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'