RV_TIMER Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: `da96c41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.980s	563.049us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.590s	34.825us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.670s	43.984us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.350s	285.313us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.750s	37.689us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.050s	27.001us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.670s	43.984us	20	20	100.00
		rv_timer_csr_aliasing	0.750s	37.689us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	8.040s	16252.391us	1	20	5.00
V2	disabled	rv_timer_disabled	3.580s	3247.890us	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	668.180s	1023646.235us	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	668.180s	1023646.235us	10	10	100.00
V2	stress	rv_timer_stress_all	6.150s	5187.404us	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.680s	12.874us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.620s	13.080us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.980s	297.652us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.980s	297.652us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.590s	34.825us	5	5	100.00
		rv_timer_csr_rw	0.670s	43.984us	20	20	100.00
		rv_timer_csr_aliasing	0.750s	37.689us	5	5	100.00
		rv_timer_same_csr_outstanding	0.730s	120.331us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.590s	34.825us	5	5	100.00
		rv_timer_csr_rw	0.670s	43.984us	20	20	100.00
		rv_timer_csr_aliasing	0.750s	37.689us	5	5	100.00
		rv_timer_same_csr_outstanding	0.730s	120.331us	20	20	100.00
V2		TOTAL			191	210	90.95
V2S	tl_intg_err	rv_timer_sec_cm	0.880s	323.293us	5	5	100.00
		rv_timer_tl_intg_err	1.170s	120.452us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.170s	120.452us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.520s	1030.851us	6	10	60.00
V3	max_value	rv_timer_max	0.990s	90.862us	1	10	10.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	54.970s	29834.130us	12	20	60.00
V3		TOTAL			19	40	47.50
		TOTAL			310	350	88.57

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.47	100.00	100.00	100.00	--	100.00	96.82	100.00

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 23 failures:
- Test rv_timer_min has 4 failures.
  - 0.rv_timer_min.38041041613761043476444458068841276810794773654258226463611376289574217715564
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 148752480 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7d6a2904) == 0x1
  UVM_INFO @ 148752480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.rv_timer_min.109100930678974716658514706743266120848197775453244665448340778207616778055861
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_min/latest/run.log
```
  UVM_FATAL @  51956912 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb485504) == 0x1
  UVM_INFO @  51956912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
- Test rv_timer_random_reset has 19 failures.
  - 1.rv_timer_random_reset.93460382809980415194905538048384694990161268440231815440954467472788160196385
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 16252390949 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5995f504) == 0x1
  UVM_INFO @ 16252390949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.rv_timer_random_reset.105192256808115322028629770578505953774006621815745417771049127071296199207283
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 977986355 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa50e4904) == 0x1
  UVM_INFO @ 977986355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 7 failures:
- Test rv_timer_max has 7 failures.
  - 0.rv_timer_max.68569048671062973653650984124101794951239246413934174452381336144453000913339
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 176212102 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 176212102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.2461535496106259493794416598100347745396590634322373741939853168409965385115
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 168929948 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 168929948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 6 failures:
- Test rv_timer_stress_all_with_rand_reset has 6 failures.
  - 4.rv_timer_stress_all_with_rand_reset.72526235100180813779457943063366987900360867964380372059824881831846403671660
    Line 131, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3606455760 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 3606455760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.rv_timer_stress_all_with_rand_reset.10418300512505823020237725299138900634419077447976765128424774431682601294371
    Line 76, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/9.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   8654151 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @   8654151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test rv_timer_stress_all_with_rand_reset has 2 failures.

5.rv_timer_stress_all_with_rand_reset.57903496685859473158490889730489260174040695428424128187608847957898697338780
Line 137, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3122751874 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3122751874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.rv_timer_stress_all_with_rand_reset.28728925994823685089967310016908259673488758421735628547890624709869537558823
Line 449, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/19.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 22408072179 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 22408072179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 2 failures:

Test rv_timer_max has 2 failures.

7.rv_timer_max.114119074299537409569433404573216021462915525848106851596779835093508869712347
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/7.rv_timer_max/latest/run.log

  UVM_ERROR @  90862402 ps: (rv_timer_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
  UVM_INFO @  90862402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.rv_timer_max.70685389773845590572974476653775681419822221137639493358616270865593851543213
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/9.rv_timer_max/latest/run.log

  UVM_ERROR @  83081310 ps: (rv_timer_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
  UVM_INFO @  83081310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---