SPI_DEVICE/1R1W Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: da96c41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	369.070s	199121.943us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.650s	81.876us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.130s	2173.838us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.090s	10421.567us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	18.430s	642.669us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.960s	128.393us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.130s	2173.838us	20	20	100.00
		spi_device_csr_aliasing	18.430s	642.669us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.000s	12.736us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.510s	143.519us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.200s	33.407us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.050s	3.048us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.820s	7.101us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	8.220s	337.157us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.220s	337.157us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	22.930s	76772.011us	50	50	100.00
		spi_device_tpm_sts_read	1.470s	233.830us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	55.500s	9133.328us	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	31.030s	8697.069us	50	50	100.00
		spi_device_flash_all	356.270s	141696.858us	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	42.500s	53020.473us	50	50	100.00
		spi_device_flash_all	356.270s	141696.858us	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	42.500s	53020.473us	50	50	100.00
		spi_device_flash_all	356.270s	141696.858us	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	356.270s	141696.858us	50	50	100.00
V2	cmd_read_status	spi_device_intercept	34.030s	7600.173us	50	50	100.00
		spi_device_flash_all	356.270s	141696.858us	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	34.030s	7600.173us	50	50	100.00
		spi_device_flash_all	356.270s	141696.858us	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	34.030s	7600.173us	50	50	100.00
		spi_device_flash_all	356.270s	141696.858us	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	34.030s	7600.173us	50	50	100.00
		spi_device_flash_all	356.270s	141696.858us	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	34.030s	7600.173us	50	50	100.00
		spi_device_flash_all	356.270s	141696.858us	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	43.600s	180646.497us	50	50	100.00
V2	mailbox_command	spi_device_mailbox	150.480s	241612.858us	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	150.480s	241612.858us	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	150.480s	241612.858us	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	34.620s	10021.598us	50	50	100.00
		spi_device_read_buffer_direct	17.070s	7004.406us	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	150.480s	241612.858us	50	50	100.00
		spi_device_flash_all	356.270s	141696.858us	50	50	100.00
V2	quad_spi	spi_device_flash_all	356.270s	141696.858us	50	50	100.00
V2	dual_spi	spi_device_flash_all	356.270s	141696.858us	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	28.930s	22970.502us	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	28.930s	22970.502us	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	369.070s	199121.943us	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	526.200s	478022.150us	50	50	100.00
V2	stress_all	spi_device_stress_all	1881.380s	260270.669us	50	50	100.00
V2	alert_test	spi_device_alert_test	1.100s	12.893us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.110s	51.199us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.480s	484.487us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.480s	484.487us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.650s	81.876us	5	5	100.00
		spi_device_csr_rw	3.130s	2173.838us	20	20	100.00
		spi_device_csr_aliasing	18.430s	642.669us	5	5	100.00
		spi_device_same_csr_outstanding	3.900s	56.435us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.650s	81.876us	5	5	100.00
		spi_device_csr_rw	3.130s	2173.838us	20	20	100.00
		spi_device_csr_aliasing	18.430s	642.669us	5	5	100.00
		spi_device_same_csr_outstanding	3.900s	56.435us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_tl_intg_err	21.750s	3357.992us	20	20	100.00
		spi_device_sec_cm	1.540s	77.127us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.750s	3357.992us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	356.810s	58442.954us	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.38	99.11	96.56	83.54	89.36	98.40	94.43	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.107730613300572521309305087833684926967654905972755497712170408157160284027490
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1911824 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[97])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1911824 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1911824 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[993])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.108670619983113896780888056049831359798846780921763456277998745020117651280619
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1768313 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[110])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1768313 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1768313 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1006])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.24403403260073658374869305988421549997727010816619728739471690520787031192253
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4567158 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3d9a58 [1111011001101001011000] vs 0x0 [0])
        UVM_ERROR @   4636158 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x26bfe1 [1001101011111111100001] vs 0x0 [0])
        UVM_ERROR @   4671158 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd32dde [110100110010110111011110] vs 0x0 [0])
        UVM_ERROR @   4764158 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2681f9 [1001101000000111111001] vs 0x0 [0])
        UVM_ERROR @   4794158 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1a6839 [110100110100000111001] vs 0x0 [0])