SPI_HOST Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: da96c41

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	147.000s	6929.803us	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	55.391us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	19.129us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	35.674us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	19.664us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	153.134us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	19.129us	20	20	100.00
		spi_host_csr_aliasing	2.000s	19.664us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	17.452us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	33.788us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	29.000s	120.082us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	39.000s	866.441us	50	50	100.00
		spi_host_error_cmd	29.000s	63.941us	50	50	100.00
		spi_host_event	709.000s	83127.485us	50	50	100.00
V2	clock_rate	spi_host_speed	32.000s	377.240us	50	50	100.00
V2	speed	spi_host_speed	32.000s	377.240us	50	50	100.00
V2	chip_select_timing	spi_host_speed	32.000s	377.240us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	383.000s	18209.956us	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	29.000s	22.115us	50	50	100.00
V2	cpol_cpha	spi_host_speed	32.000s	377.240us	50	50	100.00
V2	full_cycle	spi_host_speed	32.000s	377.240us	50	50	100.00
V2	duplex	spi_host_smoke	147.000s	6929.803us	50	50	100.00
V2	tx_rx_only	spi_host_smoke	147.000s	6929.803us	50	50	100.00
V2	stress_all	spi_host_stress_all	514.000s	1000000.000us	49	50	98.00
V2	spien	spi_host_spien	231.000s	8781.318us	50	50	100.00
V2	stall	spi_host_status_stall	1383.000s	165459.087us	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	57.000s	6924.019us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	39.000s	866.441us	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	72.013us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	27.849us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	608.496us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	608.496us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	55.391us	5	5	100.00
		spi_host_csr_rw	2.000s	19.129us	20	20	100.00
		spi_host_csr_aliasing	2.000s	19.664us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	27.336us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	55.391us	5	5	100.00
		spi_host_csr_rw	2.000s	19.129us	20	20	100.00
		spi_host_csr_aliasing	2.000s	19.664us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	27.336us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	tl_intg_err	spi_host_sec_cm	11.000s	124.416us	5	5	100.00
		spi_host_tl_intg_err	2.000s	133.341us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	133.341us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	540.000s	33584.990us	9	10	90.00
		TOTAL			838	840	99.76

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.17	96.87	93.45	98.69	94.25	88.02	100.00	95.21	90.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 2.spi_host_upper_range_clkdiv.21255553366941439097834716034297177729196807285083918563366536179487432545061
      Line 112, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_stress_all has 1 failures.

    • 19.spi_host_stress_all.104656010202711976642549025097839005191461909204953827309417040543481226516514
      Line 251, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/19.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---