SRAM_CTRL/MAIN Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: da96c41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	109.620s	278.448us	100	100	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.050s	15.588us	10	10	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.070s	99.152us	40	40	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.370s	475.624us	10	10	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.110s	20.691us	10	10	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.140s	2527.281us	40	40	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.070s	99.152us	40	40	100.00
		sram_ctrl_csr_aliasing	1.110s	20.691us	10	10	100.00
V1	mem_walk	sram_ctrl_mem_walk	347.220s	89867.656us	100	100	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	181.230s	40736.371us	100	100	100.00
V1		TOTAL			410	410	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1500.240s	78014.770us	100	100	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	390.770s	10548.666us	100	100	100.00
V2	bijection	sram_ctrl_bijection	2251.090s	117388.466us	100	100	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2061.110s	77322.375us	100	100	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	136.310s	82766.711us	100	100	100.00
V2	executable	sram_ctrl_executable	1511.520s	37890.376us	100	100	100.00
V2	partial_access	sram_ctrl_partial_access	108.070s	449.152us	100	100	100.00
		sram_ctrl_partial_access_b2b	600.740s	54804.332us	100	100	100.00
V2	max_throughput	sram_ctrl_max_throughput	117.410s	1153.807us	100	100	100.00
		sram_ctrl_throughput_w_partial_write	110.110s	282.496us	100	100	100.00
		sram_ctrl_throughput_w_readback	115.910s	576.951us	100	100	100.00
V2	regwen	sram_ctrl_regwen	1516.030s	21299.440us	100	100	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.420s	1984.597us	100	100	100.00
V2	stress_all	sram_ctrl_stress_all	8007.180s	1960274.496us	100	100	100.00
V2	alert_test	sram_ctrl_alert_test	1.050s	25.097us	100	100	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.020s	135.971us	40	40	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.020s	135.971us	40	40	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.050s	15.588us	10	10	100.00
		sram_ctrl_csr_rw	1.070s	99.152us	40	40	100.00
		sram_ctrl_csr_aliasing	1.110s	20.691us	10	10	100.00
		sram_ctrl_same_csr_outstanding	1.210s	86.948us	40	40	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.050s	15.588us	10	10	100.00
		sram_ctrl_csr_rw	1.070s	99.152us	40	40	100.00
		sram_ctrl_csr_aliasing	1.110s	20.691us	10	10	100.00
		sram_ctrl_same_csr_outstanding	1.210s	86.948us	40	40	100.00
V2		TOTAL			1580	1580	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	73.120s	29332.638us	40	40	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.170s	8.753us	0	10	0.00
		sram_ctrl_tl_intg_err	3.800s	2828.006us	40	40	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.170s	8.753us	0	10	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.800s	2828.006us	40	40	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1516.030s	21299.440us	100	100	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1516.030s	21299.440us	100	100	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.070s	99.152us	40	40	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1511.520s	37890.376us	100	100	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1511.520s	37890.376us	100	100	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1511.520s	37890.376us	100	100	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	136.310s	82766.711us	100	100	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	9.800s	9508.002us	87	100	87.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	73.120s	29332.638us	40	40	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.580s	13143.987us	77	100	77.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	109.620s	278.448us	100	100	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	109.620s	278.448us	100	100	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1511.520s	37890.376us	100	100	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.170s	8.753us	0	10	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	136.310s	82766.711us	100	100	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.170s	8.753us	0	10	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.170s	8.753us	0	10	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	109.620s	278.448us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.170s	8.753us	0	10	0.00
V2S		TOTAL			244	290	84.14
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	640.680s	56873.794us	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			2334	2380	98.07

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.41	99.11	92.90	90.71	100.00	98.02	95.83	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 23 failures:

  • Test sram_ctrl_readback_err has 23 failures.

    • 2.sram_ctrl_readback_err.9516800332026930033400020527627559282976546893675340733053759280473674050242
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1369372420 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6a) != exp (0x2a)
        UVM_INFO @ 1369372420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 8.sram_ctrl_readback_err.4273060904901722295090908517296793302600428764946644301127520937030602027540
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/8.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 675372191 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1c) != exp (0x49)
        UVM_INFO @ 675372191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 21 more failures.

• Offending 'reqfifo_rvalid' has 13 failures:

  • Test sram_ctrl_mubi_enc_err has 13 failures.

    • 0.sram_ctrl_mubi_enc_err.25822186034403395157874871263037696337907461203630058929247872013070551289845
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 708163529 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 708163529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_mubi_enc_err.32900380705927005774393805872003729266879117831808704685881260869199449891186
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2639675360 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2639675360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 11 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 8 failures:

  • Test sram_ctrl_sec_cm has 8 failures.

    • 0.sram_ctrl_sec_cm.30253705086560439608211342187090379024916856671499222104199752522224708366245
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3358627 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3358627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.56732082025821970911706397434037710126383739929929459156190447019013528267768
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  10367131 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  10367131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.86103959068140645038726871504048069917154758899258419265443968048090905041042
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  10484373 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  10484373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.44513125723855793255080354192095134426164155867196918409381659970295965644848
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @  20820032 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @  20820032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---