UART Simulation Results

Friday December 05 2025 17:02:05 UTC

GitHub Revision: `da96c41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	24.690s	5879.721us	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.930s	26.593us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.970s	14.506us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.910s	114.509us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.110s	310.201us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.460s	24.242us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.970s	14.506us	20	20	100.00
		uart_csr_aliasing	1.110s	310.201us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	272.750s	77056.582us	49	50	98.00
V2	parity	uart_smoke	24.690s	5879.721us	50	50	100.00
		uart_tx_rx	272.750s	77056.582us	49	50	98.00
V2	parity_error	uart_intr	1271.330s	799710.364us	50	50	100.00
		uart_rx_parity_err	375.940s	168014.909us	50	50	100.00
V2	watermark	uart_tx_rx	272.750s	77056.582us	49	50	98.00
		uart_intr	1271.330s	799710.364us	50	50	100.00
V2	fifo_full	uart_fifo_full	472.540s	162606.085us	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	365.100s	210235.435us	49	50	98.00
V2	fifo_reset	uart_fifo_reset	335.610s	249044.885us	299	300	99.67
V2	rx_frame_err	uart_intr	1271.330s	799710.364us	50	50	100.00
V2	rx_break_err	uart_intr	1271.330s	799710.364us	50	50	100.00
V2	rx_timeout	uart_intr	1271.330s	799710.364us	50	50	100.00
V2	perf	uart_perf	1308.900s	30648.153us	49	50	98.00
V2	sys_loopback	uart_loopback	23.980s	8764.917us	50	50	100.00
V2	line_loopback	uart_loopback	23.980s	8764.917us	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	98.250s	57293.190us	6	50	12.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	86.670s	45169.376us	50	50	100.00
V2	tx_overide	uart_tx_ovrd	30.330s	13143.371us	50	50	100.00
V2	rx_oversample	uart_rx_oversample	61.120s	6618.018us	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	967.680s	209876.824us	50	50	100.00
V2	stress_all	uart_stress_all	2511.990s	389615.078us	39	50	78.00
V2	alert_test	uart_alert_test	0.930s	26.724us	50	50	100.00
V2	intr_test	uart_intr_test	0.910s	16.018us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.510s	133.710us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.510s	133.710us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.930s	26.593us	5	5	100.00
		uart_csr_rw	0.970s	14.506us	20	20	100.00
		uart_csr_aliasing	1.110s	310.201us	5	5	100.00
		uart_same_csr_outstanding	1.050s	246.533us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.930s	26.593us	5	5	100.00
		uart_csr_rw	0.970s	14.506us	20	20	100.00
		uart_csr_aliasing	1.110s	310.201us	5	5	100.00
		uart_same_csr_outstanding	1.050s	246.533us	20	20	100.00
V2		TOTAL			1031	1090	94.59
V2S	tl_intg_err	uart_sec_cm	1.300s	190.464us	5	5	100.00
		uart_tl_intg_err	1.680s	329.447us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.680s	329.447us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	109.780s	42714.051us	88	100	88.00
V3		TOTAL			88	100	88.00
		TOTAL			1249	1320	94.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.34	99.48	98.25	91.55	--	98.14	97.12	99.53

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 39 failures:

Test uart_noise_filter has 23 failures.

0.uart_noise_filter.24529676607368437048680113135997176556460589519115053091557372256271406618033
Line 83, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

  UVM_ERROR @ 101363245160 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 101363245160 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 103734226192 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 103734226192 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 103734226192 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1

6.uart_noise_filter.90370264735214821529634803935766335312350600216991625146819678770429537683546
Line 80, in log /nightly/current_run/scratch/master/uart-sim-vcs/6.uart_noise_filter/latest/run.log

  UVM_ERROR @ 42986491615 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 42986491615 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 44029874962 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 44029874962 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 44139125836 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1

... and 21 more failures.

Test uart_stress_all has 9 failures.

4.uart_stress_all.70569620724312895330227276702082728234847270809491847702162527931132162973723
Line 124, in log /nightly/current_run/scratch/master/uart-sim-vcs/4.uart_stress_all/latest/run.log

  UVM_ERROR @ 100357966425 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 100357966425 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 100365966425 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 100384856425 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 100384876425 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0

9.uart_stress_all.78748328557528299081540049575618959191775315237556172907546967380813975107569
Line 92, in log /nightly/current_run/scratch/master/uart-sim-vcs/9.uart_stress_all/latest/run.log

  UVM_ERROR @ 10284299913 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 10284728481 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 10285371333 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 10285692759 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 10285978471 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

... and 7 more failures.

Test uart_stress_all_with_rand_reset has 7 failures.

12.uart_stress_all_with_rand_reset.73225807290832853847279607159957213083823850721024960848718824346229278864706
Line 170, in log /nightly/current_run/scratch/master/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2308059845 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 2308304519 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_INFO @ 2311985267 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/791
  UVM_INFO @ 2324331774 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 10/10

18.uart_stress_all_with_rand_reset.32723829837628245794105102928175517730575086982340401027811449550917452034918
Line 91, in log /nightly/current_run/scratch/master/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 634727355 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 634727355 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_INFO @ 708565665 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/41
  UVM_INFO @ 777636303 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/41
  UVM_INFO @ 811080714 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/41

... and 5 more failures.

UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 16 failures:

Test uart_noise_filter has 13 failures.

1.uart_noise_filter.22465333262656305461089939698220212351366816602360897177092218450193717850550
Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log

  UVM_ERROR @ 2885616053 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 2885626154 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 2885636255 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 123 [0x7b]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 2885646356 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 2885686760 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata

2.uart_noise_filter.50554694053950752806651256627988574861043882213536946588081870096364889529359
Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/2.uart_noise_filter/latest/run.log

  UVM_ERROR @ 23018840356 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7,                                 clk_pulses: 0
  UVM_ERROR @ 23018923689 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 23019007022 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 23019090355 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 23019173688 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata

... and 11 more failures.

Test uart_stress_all_with_rand_reset has 2 failures.

38.uart_stress_all_with_rand_reset.39478797359362516103188797424274954548257968845866157552239043562533287797167
Line 78, in log /nightly/current_run/scratch/master/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 357766004 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 357796931 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 357807240 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 207 [0xcf]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 357848476 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 357879403 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

78.uart_stress_all_with_rand_reset.66638218260898872029268516738709616047740379685422840009243807183351725430062
Line 117, in log /nightly/current_run/scratch/master/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6538336777 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 6538375239 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 6538490625 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
  UVM_INFO @ 6607606839 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/286
  UVM_ERROR @ 6612337665 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

Test uart_stress_all has 1 failures.

41.uart_stress_all.98643635435761631440814094767722999872459521766346684099254056779283493191492
Line 132, in log /nightly/current_run/scratch/master/uart-sim-vcs/41.uart_stress_all/latest/run.log

  UVM_ERROR @ 201945546892 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 201945588559 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 201945630226 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (189 [0xbd] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 201945671893 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 201945713560 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (189 [0xbd] vs 255 [0xff]) reg name: uart_reg_block.rdata

UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 7 failures:

Test uart_noise_filter has 6 failures.

5.uart_noise_filter.86405750891719877015964539643153715802408804288812520491971256421570592986138
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/5.uart_noise_filter/latest/run.log

  UVM_ERROR @ 634321609 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 634321609 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 634321609 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 797447914 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 10,                                 clk_pulses: 0
  UVM_ERROR @ 797531248 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (134 [0x86] vs 255 [0xff]) reg name: uart_reg_block.rdata

11.uart_noise_filter.96978722689405411210818290358305631910683867363939144868669431584250248643495
Line 77, in log /nightly/current_run/scratch/master/uart-sim-vcs/11.uart_noise_filter/latest/run.log

  UVM_ERROR @ 920236662 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 920236662 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 920236662 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 1364996662 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 1654156662 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 15,                                 clk_pulses: 0

... and 4 more failures.

Test uart_stress_all has 1 failures.

28.uart_stress_all.74428176614631567361094444537319454691239188814689733351481209232085549238303
Line 80, in log /nightly/current_run/scratch/master/uart-sim-vcs/28.uart_stress_all/latest/run.log

  UVM_ERROR @ 398482464 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 398482464 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 466624776 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 466660490 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 466696204 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata

UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 3 failures:

Test uart_perf has 1 failures.

27.uart_perf.22756327738928835781823161847393254656810067094646263762769455260514529248734
Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/27.uart_perf/latest/run.log

  UVM_ERROR @ 5076097734 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @ 9680193156 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/7
  UVM_INFO @ 13043927734 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/7
  UVM_INFO @ 20335837734 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/7
  UVM_INFO @ 27818422110 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 6/7

Test uart_fifo_overflow has 1 failures.

37.uart_fifo_overflow.49458509537636773532450084654792528476610884982832884426892899067245749761840
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/37.uart_fifo_overflow/latest/run.log

  UVM_ERROR @   4468485 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @ 2651654097 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/5
  UVM_INFO @ 3392355293 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/5
  UVM_INFO @ 3638973637 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/5
  UVM_INFO @ 5058713128 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/5

Test uart_fifo_reset has 1 failures.

123.uart_fifo_reset.89761508212158783053469238569419888046853560400453347430721690265586310726445
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/123.uart_fifo_reset/latest/run.log

  UVM_ERROR @  11491506 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @ 114169616506 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/6
  UVM_INFO @ 118640491506 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/6
  UVM_INFO @ 120872866506 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/6
  UVM_INFO @ 125032241506 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/6

UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 2 failures:

Test uart_noise_filter has 1 failures.

16.uart_noise_filter.25536273601725112795891671442082815987440666379760903651322150802322369802503
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/16.uart_noise_filter/latest/run.log

  UVM_ERROR @  35322516 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @  35322516 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_ERROR @  36669444 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @  36669444 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_ERROR @ 263667628 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5,                                 clk_pulses: 0

Test uart_stress_all_with_rand_reset has 1 failures.

24.uart_stress_all_with_rand_reset.89239161951240939152587470487183061754646228108763610100499895310307052011458
Line 97, in log /nightly/current_run/scratch/master/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3082964499 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 3082964499 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_ERROR @ 3169516829 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 3169516829 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 3169516829 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1

UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

41.uart_stress_all_with_rand_reset.3381012156238376232950233774789846870729530858210744051291138010569885647027
Line 109, in log /nightly/current_run/scratch/master/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2766626277 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 2766626277 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
  UVM_ERROR @ 2767501277 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
  UVM_ERROR @ 2767595027 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 2767626277 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata

81.uart_stress_all_with_rand_reset.26633254893051421078619269405964434722020930034714183290845722059416977267508
Line 130, in log /nightly/current_run/scratch/master/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2003323569 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 2004417354 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 2011823841 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 2011823841 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 2014730184 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0

UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr has 1 failures:

Test uart_noise_filter has 1 failures.

41.uart_noise_filter.47625719566059884241198584122584879871875186305649612953550586586189967666792
Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/41.uart_noise_filter/latest/run.log

  UVM_ERROR @ 16083947997 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 16083947997 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 16377427997 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 16418587997 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 16418587997 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 1 failures:

Test uart_tx_rx has 1 failures.

49.uart_tx_rx.114106224355251749085271229893644891736286085790617713482409812071879628724531
Line 76, in log /nightly/current_run/scratch/master/uart-sim-vcs/49.uart_tx_rx/latest/run.log

  UVM_ERROR @  32057479 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
  UVM_INFO @ 5400623539 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 1/7
  UVM_INFO @ 8478477604 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 2/7
  UVM_INFO @ 11774760022 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 3/7
  UVM_INFO @ 13905615034 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 4/7