da96c41| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 89.299s | 0.000us | 0 | 5 | 0.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 89.299s | 0.000us | 0 | 5 | 0.00 |
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 20.019s | 0.000us | 0 | 20 | 0.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 25.235s | 0.000us | 0 | 5 | 0.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 403.340s | 270.958us | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 403.340s | 270.958us | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 403.340s | 270.958us | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_rom | 50.090s | 10.180us | 0 | 3 | 0.00 |
| chip_sw_example_manufacturer | 200.214s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_example_concurrency | 226.950s | 150.357us | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 14.059s | 0.000us | 0 | 3 | 0.00 | ||
| V1 | csr_bit_bash | chip_csr_bit_bash | 12.430s | 0.000us | 0 | 3 | 0.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 15.550s | 0.000us | 0 | 3 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 15.550s | 0.000us | 0 | 3 | 0.00 |
| V1 | xbar_smoke | xbar_smoke | 37.610s | 61.648us | 100 | 100 | 100.00 |
| V1 | TOTAL | 106 | 151 | 70.20 | |||
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 17.138s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 3474.750s | 3708.885us | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 446.370s | 357.887us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 14.104s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 22.676s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 15.786s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 18.034s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 4.120s | 0.000us | 0 | 10 | 0.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 4.120s | 0.000us | 0 | 10 | 0.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 144.780s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 126.154s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 148.411s | 0.000us | 0 | 6 | 0.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 148.411s | 0.000us | 0 | 6 | 0.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 141.670s | 117.017us | 0 | 3 | 0.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 148.150s | 117.020us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 350.890s | 272.327us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 15.507s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 16.014s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 304.120s | 377.641us | 0 | 3 | 0.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 311.580s | 248.788us | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 660.890s | 602.553us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 660.890s | 602.553us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 478.530s | 348.730us | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 270.310s | 164.340us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 270.310s | 164.340us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 413.450s | 2271.509us | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 198.250s | 145.517us | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 375.790s | 225.619us | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 248.590s | 147.267us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 239.250s | 161.567us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 215.820s | 145.030us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 211.980s | 165.696us | 0 | 3 | 0.00 |
| chip_sw_clkmgr_off_hmac_trans | 228.630s | 165.664us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 234.900s | 165.664us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 239.520s | 165.616us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_otbn_ecdsa_op_irq_jitter_en | 59.390s | 10.400us | 0 | 3 | 0.00 |
| chip_sw_aes_enc_jitter_en | 64.930s | 10.200us | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en | 61.730s | 10.140us | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 71.140s | 10.180us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 57.250s | 10.180us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 17.340s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_jitter | 196.200s | 141.908us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 497.770s | 1779.398us | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 58.200s | 10.160us | 0 | 3 | 0.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 65.960s | 10.240us | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 51.110s | 10.400us | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 53.890s | 10.320us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 57.390s | 10.380us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 57.070s | 10.360us | 0 | 3 | 0.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 58.640s | 10.200us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 14.676s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 18.535s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 18.544s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 1470.990s | 905.545us | 0 | 100 | 0.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 480.700s | 504.310us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 270.310s | 164.340us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 18.230s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 480.700s | 504.310us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 15.242s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 15.467s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 15.078s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 15.273s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 15.088s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 1470.990s | 905.545us | 0 | 100 | 0.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 350.890s | 272.327us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 443.210s | 375.344us | 0 | 3 | 0.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 395.750s | 267.260us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 426.090s | 290.101us | 0 | 3 | 0.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 232.200s | 144.087us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 1470.990s | 905.545us | 0 | 100 | 0.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 16.242s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 15.817s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 1470.990s | 905.545us | 0 | 100 | 0.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 16.839s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 426.090s | 290.101us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 355.970s | 253.194us | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 18.250s | 0.000us | 0 | 90 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 14.963s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 14.266s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 14.854s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 15.287s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 15.817s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_sw_lc_ctrl_transition | 17.499s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 21.897s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 17.499s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 17.499s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 17.499s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_dpe_key_derivation_prod | 309.500s | 267.664us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_prim_tl_access | 725.930s | 1092.226us | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 304.120s | 377.641us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 18.718s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 16.874s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 17.314s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 15.814s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_ctrl_transition | 17.499s | 0.000us | 0 | 15 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation | 339.350s | 267.632us | 0 | 3 | 0.00 | ||
| chip_sw_rom_ctrl_integrity_check | 1116.910s | 1266.559us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 16.125s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 237.930s | 157.071us | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 64.930s | 10.200us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 207.310s | 145.857us | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 248.590s | 147.267us | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 224.520s | 156.417us | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 61.730s | 10.140us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 239.250s | 161.567us | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 231.390s | 148.918us | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 281.200s | 172.115us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 57.250s | 10.180us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_dpe_key_derivation | 339.350s | 267.632us | 0 | 3 | 0.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 17.499s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 47.750s | 10.120us | 0 | 3 | 0.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 332.610s | 203.341us | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 215.820s | 145.030us | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 503.520s | 272.983us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 503.520s | 272.983us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 15.871s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 264.470s | 156.782us | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 3139.010s | 1873.435us | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_dpe_key_derivation | chip_sw_keymgr_dpe_key_derivation | 339.350s | 267.632us | 0 | 3 | 0.00 |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 71.140s | 10.180us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 3810.960s | 1454.804us | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 59.390s | 10.400us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 375.790s | 225.619us | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 375.790s | 225.619us | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 375.790s | 225.619us | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 503.880s | 264.584us | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 1116.910s | 1266.559us | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 1116.910s | 1266.559us | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 482.670s | 314.247us | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 17.340s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 16.125s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 1470.990s | 905.545us | 0 | 100 | 0.00 |
| chip_sw_data_integrity_escalation | 148.411s | 0.000us | 0 | 6 | 0.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 17.499s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_otbn_mem_scramble | 503.880s | 264.584us | 3 | 3 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 339.350s | 267.632us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 482.670s | 314.247us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 203.540s | 155.636us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_otbn_mem_scramble | 503.880s | 264.584us | 3 | 3 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 339.350s | 267.632us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 482.670s | 314.247us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 203.540s | 155.636us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 17.499s | 0.000us | 0 | 15 | 0.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 14.471s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 21.897s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_prim_tl_access | 725.930s | 1092.226us | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 18.718s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 16.874s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 17.314s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 15.814s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_ctrl_transition | 17.499s | 0.000us | 0 | 15 | 0.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 725.930s | 1092.226us | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_nvm_cnt | chip_sw_otp_ctrl_nvm_cnt | 14.215s | 0.000us | 0 | 1 | 0.00 |
| V2 | chip_sw_otp_ctrl_sw_parts | chip_sw_otp_ctrl_sw_parts | 15.496s | 0.000us | 0 | 1 | 0.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 14.676s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_otbn_ecdsa_op_irq_jitter_en | 59.390s | 10.400us | 0 | 3 | 0.00 |
| chip_sw_aes_enc_jitter_en | 64.930s | 10.200us | 0 | 3 | 0.00 | ||
| chip_sw_hmac_enc_jitter_en | 61.730s | 10.140us | 0 | 3 | 0.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 71.140s | 10.180us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 57.250s | 10.180us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 17.340s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_jitter | 196.200s | 141.908us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_soc_proxy_external_reset_requests | chip_sw_soc_proxy_smoketest | 228.210s | 143.472us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_external_irqs | chip_sw_soc_proxy_smoketest | 228.210s | 143.472us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_external_wakeup_requests | chip_sw_soc_proxy_external_wakeup | 226.480s | 138.779us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_gpios | chip_sw_soc_proxy_gpios | 182.050s | 136.478us | 0 | 3 | 0.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 438.270s | 251.622us | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 313.770s | 193.981us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 229.960s | 164.760us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 203.540s | 155.636us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 443.210s | 375.344us | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 443.210s | 375.344us | 0 | 3 | 0.00 |
| V2 | chip_sw_smoketest | chip_sw_aes_smoketest | 234.390s | 157.112us | 3 | 3 | 100.00 |
| chip_sw_aon_timer_smoketest | 232.320s | 163.267us | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 218.010s | 142.987us | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 230.780s | 144.809us | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 243.360s | 174.132us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 268.900s | 182.014us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 265.500s | 171.089us | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 340.950s | 220.774us | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 207.990s | 146.936us | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 202.020s | 145.067us | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 297.400s | 248.724us | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 204.870s | 141.654us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 207.800s | 145.499us | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 236.920s | 157.839us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 13.831s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 14.059s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 17.138s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_secure_boot | base_rom_e2e_smoke | 18.658s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 210.890s | 196.521us | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 242.800s | 231.995us | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 253.850s | 223.550us | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 250.820s | 217.185us | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_rv_dm_lc_disabled | 304.120s | 377.641us | 0 | 3 | 0.00 |
| chip_sw_lc_walkthrough_testunlocks | 15.198s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 14.667s | 0.000us | 0 | 3 | 0.00 |
| chip_sw_lc_walkthrough_prod | 13.930s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_prodend | 15.094s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_rma | 15.559s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 15.198s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 675.780s | 654.477us | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 737.810s | 790.145us | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 14.889s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 14.043s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 21.202s | 0.000us | 0 | 3 | 0.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 42.660s | 0.000us | 0 | 3 | 0.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 171.800s | 118.302us | 0 | 30 | 0.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 171.800s | 118.302us | 0 | 30 | 0.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 15.550s | 0.000us | 0 | 3 | 0.00 |
| chip_same_csr_outstanding | 15.840s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 15.550s | 0.000us | 0 | 3 | 0.00 |
| chip_same_csr_outstanding | 15.840s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 269.980s | 526.389us | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 15.500s | 13.407us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 630.950s | 2800.504us | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 603.840s | 2010.743us | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 137.680s | 79.448us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 2366.130s | 14313.745us | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 3512.460s | 15286.611us | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 187.980s | 224.949us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 188.080s | 257.091us | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 269.970s | 503.436us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 188.080s | 257.091us | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 549.160s | 875.077us | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 3529.440s | 15132.487us | 69 | 100 | 69.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 262.010s | 480.172us | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 1840.620s | 3654.768us | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 2300.840s | 4834.603us | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 3522.520s | 1826.858us | 95 | 100 | 95.00 |
| xbar_stress_all_with_reset_error | 3373.250s | 5491.035us | 93 | 100 | 93.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 18.336s | 0.000us | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 15.875s | 0.000us | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 16.780s | 0.000us | 0 | 3 | 0.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 15.809s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 13.931s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 14.670s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 13.173s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 12.889s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 13.384s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 14.126s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 11.179s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 12.919s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 11.903s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 75.456s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 77.684s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 65.449s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 74.556s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 82.527s | 0.000us | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 61.472s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 89.379s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 76.051s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 63.719s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 46.666s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 77.818s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 68.541s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 64.790s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 68.386s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 38.273s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 11.966s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 12.571s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 18.363s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 15.346s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 12.216s | 0.000us | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 16.874s | 0.000us | 0 | 3 | 0.00 |
| rom_e2e_asm_init_dev | 15.907s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod | 17.879s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod_end | 14.908s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_rma | 14.285s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 14.493s | 0.000us | 0 | 3 | 0.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 15.336s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 14.519s | 0.000us | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 13.727s | 0.000us | 0 | 3 | 0.00 |
| V2 | TOTAL | 1812 | 2405 | 75.34 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 283.710s | 174.075us | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 198.820s | 136.952us | 2 | 3 | 66.67 |
| V2S | TOTAL | 5 | 6 | 83.33 | |||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 14.164s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 13.231s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 12.821s | 0.000us | 0 | 1 | 0.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 16.140s | 0.000us | 0 | 3 | 0.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 1470.990s | 905.545us | 0 | 100 | 0.00 |
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 16.350s | 0.000us | 0 | 3 | 0.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 201.360s | 158.112us | 0 | 1 | 0.00 |
| V3 | chip_sw_coremark | chip_sw_coremark | 14.045s | 0.000us | 0 | 1 | 0.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 14.817s | 0.000us | 0 | 3 | 0.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 14.164s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 13.231s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 12.821s | 0.000us | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 11.823s | 0.000us | 0 | 1 | 0.00 |
| rom_e2e_jtag_inject_dev | 13.434s | 0.000us | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_inject_rma | 11.246s | 0.000us | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 14.728s | 0.000us | 0 | 3 | 0.00 |
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 1326.350s | 905.585us | 0 | 3 | 0.00 | |
| chip_sw_entropy_src_kat_test | 218.850s | 144.317us | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_ast_rng_req | 228.340s | 141.544us | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_0 | 615.370s | 346.697us | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_10 | 546.850s | 302.066us | 3 | 3 | 100.00 | ||
| chip_sw_dma_inline_hashing | 275.700s | 191.485us | 3 | 3 | 100.00 | ||
| chip_sw_dma_abort | 276.240s | 192.882us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 13.274s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 13.518s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 14.456s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 13.629s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 14.402s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 14.637s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 14.688s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 13.927s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 14.704s | 0.000us | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 14.226s | 0.000us | 0 | 3 | 0.00 | ||
| chip_sw_entropy_src_smoketest | 289.300s | 170.772us | 3 | 3 | 100.00 | ||
| chip_sw_mbx_smoketest | 562.820s | 397.708us | 3 | 3 | 100.00 | ||
| TOTAL | 1944 | 2639 | 73.66 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 72.22 | 71.90 | 77.99 | 63.84 | 57.14 | 80.20 | 68.24 | 86.20 |
Job returned non-zero exit code has 399 failures:
0.chip_sw_example_manufacturer.64420033102563430867579549160742079013438034288181520172972157738242792849672
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log
Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 181.502s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_example_manufacturer.52993025117053377973945246111056017832294568098164099749263228678147470471265
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log
Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 33.736s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_data_integrity_escalation.14781548797413746105399001305732569585520850671238729880085870706456995184500
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log
Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 136.779s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_data_integrity_escalation.55560991077267230518302786590245688682928528600856741744841654020563650478718
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log
Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.203s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 4 more failures.
0.chip_sw_sleep_pin_wake.32018276397157545661707845521308124847236037529017929449335542412833664879198
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 129.732s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_sleep_pin_wake.28195392247394953652934340779106161894151160524903447020971915263981688903583
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 27.200s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_sleep_pin_retention.55765635304382733351407335853132370517972201210432958925170607816030055626899
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 111.174s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_sleep_pin_retention.23776131196532413654382991761077586383940256743841651526143306757524389227904
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log
Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 17.710s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.chip_sw_uart_tx_rx.32144214305724532047239236154817033070936603674948544857332967988079596604288
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log
Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 74.190s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_uart_tx_rx.47501625588882933408515267379731761997669738034969179908348061833787106562885
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log
Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 10.723s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 3 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 93 failures:
0.chip_sw_all_escalation_resets.1957562703614150986260664247969907651924549003455431617359621550489420469286
Line 449, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 905.594000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.594000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_all_escalation_resets.19187272185028607199740662408244526226214333208201095528426383945360330080504
Line 526, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 905.485000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.485000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 88 more failures.
0.chip_sw_rstmgr_rst_cnsty_escalation.102122176957665854024645664419783873860539227953718571769808046236160892030338
Line 430, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
UVM_ERROR @ 905.588000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.588000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_rst_cnsty_escalation.12314325943141356624041429843626024270396150763241846301924848365457609272092
Line 508, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
UVM_ERROR @ 905.585000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 905.585000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job timed out after * minutes has 43 failures:
0.xbar_access_same_device_slow_rsp.86266462777492644388708019211705753762773956274473412710174661281992519599581
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log
Job timed out after 60 minutes
9.xbar_access_same_device_slow_rsp.34642759564096267234476609987477028431617162688278177959859539030771924102318
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.xbar_access_same_device_slow_rsp/latest/run.log
Job timed out after 60 minutes
... and 29 more failures.
19.xbar_stress_all_with_rand_reset.104272475363559513149511242883716089749680328164269135038249725560021807714612
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.xbar_stress_all_with_rand_reset/latest/run.log
Job timed out after 60 minutes
65.xbar_stress_all_with_rand_reset.33543027524992543358208238927144919104946008444527583030851736456824966438073
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/65.xbar_stress_all_with_rand_reset/latest/run.log
Job timed out after 60 minutes
... and 3 more failures.
26.xbar_stress_all_with_reset_error.16462878060323054876279748487314403721009265150702167091891238607464151751695
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/26.xbar_stress_all_with_reset_error/latest/run.log
Job timed out after 60 minutes
27.xbar_stress_all_with_reset_error.115078456919103368549305687222923312071307469978353871203374166654970518868753
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.xbar_stress_all_with_reset_error/latest/run.log
Job timed out after 60 minutes
... and 5 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 36 failures:
0.chip_sw_otbn_ecdsa_op_irq_jitter_en.114942172787702261818310563142161639453261443788860219523525528473596947596446
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
UVM_FATAL @ 10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_otbn_ecdsa_op_irq_jitter_en.15787212492616108048723008572916493489148699820367929311300553222269311308518
Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
UVM_FATAL @ 10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_aes_enc_jitter_en.96620283325048790575862348313230993905144878756403031495842765975219614723057
Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aes_enc_jitter_en.73109028721847588556668261982044008608410135433315717125112932586797771942755
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_hmac_enc_jitter_en.36607617192492939489239291886177677468272592582289462272900336815148068271043
Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_hmac_enc_jitter_en.78901006488170886601300700600631505351948950450642660570660657212551006610974
Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_dpe_key_derivation_jitter_en.44570873029166730991190929525917772970973566662303109684914400358777619872361
Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
UVM_FATAL @ 10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation_jitter_en.83762169732679294378173430098015421363242980763864563250259673301196128209607
Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
UVM_FATAL @ 10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_kmac_mode_kmac_jitter_en.34414657985091984196483382270548453650737586086047228238277126293041018564869
Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
UVM_FATAL @ 10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_kmac_mode_kmac_jitter_en.60855901447211204452675861676747795122750643911906666771696231820170724646562
Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
UVM_FATAL @ 10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 26 failures:
0.chip_tl_errors.68826256534527474125097026430887095962261156493610042970824833775543983673770
Line 229, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
UVM_ERROR @ 118.105000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
UVM_INFO @ 118.105000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_tl_errors.75937081053243969602304074505248920385557747048114691789381798013863531558588
Line 229, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log
Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
UVM_ERROR @ 118.342000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
UVM_INFO @ 118.342000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 17 failures:
0.chip_sw_rstmgr_cpu_info.85387302625715792832001046803448498855070830581504055936658514081246868865752
Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 375.296000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 375.296000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_cpu_info.39957543948637503956641758651164294215177928512929120390802412706324169647981
Line 421, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 375.344000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 375.344000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_aes_trans.38846793696177575182300631341332028701116183471382210398331726633870999287310
Line 433, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.696000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.696000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_aes_trans.59550484712383555147910397813585752839144040923612331960547245038551771257596
Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.696000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.696000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_hmac_trans.46480591951729796482117702773706734249197152040631936993789744456758177879813
Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_hmac_trans.62726822564139351773731549802858231893656965195493762558198754801811256933722
Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_kmac_trans.9439511174571533216442828901990549893461357030809754986166652755107746665909
Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.680000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_kmac_trans.15675019793710911928516686275736818484837503957764581061578576185974882962706
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_otbn_trans.81419623623148256163761439764728464711156857310621933999997573438638480639403
Line 408, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.616000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.616000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_otbn_trans.63956450767872836764148069160388936084688918989587815150285358480514527248858
Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 165.680000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 165.680000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
0.chip_padctrl_attributes.95032389175397216586399418980752956025742358120486723634743783392369472974203
Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 92
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
1.chip_padctrl_attributes.87815564314912137813535241785897762549691206902918044141372519418813074513277
Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 92
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
0.chip_csr_bit_bash.93457086057764138056752222869600125915679767598919199336255313925495519269823
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_bit_bash.51389452063876105791519485368363149001115456310300458051752525161334241014578
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_csr_aliasing.95747313121721423425877645340157139032655287987183884956095552143222953049963
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_aliasing.8794342940778723036560863977283368479479215390230921185023543969972217854716
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_same_csr_outstanding.112833583034636192559349884447490868943175597430359888729823411289212647011513
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_same_csr_outstanding.111760485364259646290393987385837952082711010937827322632175922062173123816489
Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 6 failures:
0.chip_sw_keymgr_dpe_key_derivation.30052738657275536464643240711957303942196677725569305397590951989704261999500
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
UVM_ERROR @ 267.693000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (6894950045972027862992101548016687391922173467918979183946790967058427693333199217782905927431264293394648868688832352903575131917594279725761990005972060 [0x83a5d054aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd305f360a57f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 267.693000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation.92769821704570769756567208080160785837692322499146446215675024196402017798220
Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log
UVM_ERROR @ 267.632000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (3206463364766303642577054730652178338431979640824268577662591327296270597029909623954384548657772011182245978400050508360601859360816582443795827394960476 [0x3d38ddcfaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3bb6e6d3e7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 267.632000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_dpe_key_derivation_prod.68753860250969044628209020858151721091588023679800037360854987320657721747378
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
UVM_ERROR @ 267.712000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1612598628868235488996572584982183102249008811990193719014088875706210497730352894052015619851603916830566512909508723061200180641652986485107916628384860 [0x1eca37c8aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3989c87397f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 267.712000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation_prod.105062212913820811605890156707695609976874543648410391512899323024541058899152
Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
UVM_ERROR @ 267.789000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (6792630544727118143231002953325136754028914543425829155421126493858909357719137047610754514729663668293934149442266266991754924692872092657399513590619228 [0x81b1afbdaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd307e71f4c7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 267.789000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41768) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:
0.chip_jtag_csr_rw.114374017681166492772975897342662378795948392527262557749064493777667628923000
Line 5959, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 116.989000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41768) { a_addr: 'h30480000 a_data: 'h89b693b5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h1 a_user: 'h248f2 d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 116.989000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_jtag_csr_rw.76661953251581129298208559065405966980076882237031173816819998885737965168985
Line 5959, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 117.017000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41768) { a_addr: 'h30480000 a_data: 'h9a98093b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h1 a_user: 'h248af d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.017000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_jtag_mem_access.71631196535288237290264948164215570639062252571737294347804155813889121646322
Line 5959, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.020000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41768) { a_addr: 'h30480000 a_data: 'h25e5e3f2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h1 a_user: 'h248e7 d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.020000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_jtag_mem_access.19342255874134351223934166779644269590490590293826998451411144661511460371175
Line 5959, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.029000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41768) { a_addr: 'h30480000 a_data: 'h2c1ccc66 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h0 a_user: 'h26926 d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.029000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 3 failures:
0.chip_rv_dm_lc_disabled.24954761959522600889159345517520585589478642506558664500310332387107937366927
Line 202, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 123.591000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40714 read out mismatch
UVM_INFO @ 123.591000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_rv_dm_lc_disabled.40906882062048073139214930820691400595334225603732361475111771957736303539599
Line 218, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 377.641000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40480 read out mismatch
UVM_INFO @ 377.641000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:
0.chip_sw_example_rom.33052131575969083888713011908042411725558501022050861824685585556921868713616
Line 579, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_example_rom.43194896850568905410505080569772546448153332726295635470068926790224048114960
Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
0.chip_sw_spi_device_pass_through_collision.36557057686431660800972355181734663250346059779091589283933591786116894386797
Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_ERROR @ 357.887000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 357.887000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_spi_device_pass_through_collision.77432318382336348578216158839636467911411521636813485288423225985226484554982
Line 433, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_ERROR @ 163.945000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 163.945000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 3 failures:
Test chip_sw_otp_ctrl_escalation has 1 failures.
0.chip_sw_otp_ctrl_escalation.18236101387583836931899521549380337447714168593516116997769741694294170293493
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 158.112000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 158.112000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_all_escalation_resets has 2 failures.
56.chip_sw_all_escalation_resets.24743900366884552672376528654815212606221115746116299672832231565600473402629
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 158.028000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 158.028000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
76.chip_sw_all_escalation_resets.91811556415610315935330609826255500644778821329339007579707670853722724328312
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 158.008000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 158.008000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size has 3 failures:
0.chip_sw_rstmgr_alert_info.115555519894154239029932772269430341093302069859357917605449200019964969100573
Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
UVM_ERROR @ 289.850000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 289.850000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_alert_info.114957974801992880747645383740116996660432247280217665906400720950914234843338
Line 417, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log
UVM_ERROR @ 289.941000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:66)] CHECK-fail: word_index < dump_size
UVM_INFO @ 289.941000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:
0.chip_sw_soc_proxy_external_wakeup.4294294202169523774281881463393344174865283037379348472477172258716519009160
Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
UVM_ERROR @ 138.824000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 138.824000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_external_wakeup.44833312300298672022574719375826585088982791770230111280358157610684099912738
Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log
UVM_ERROR @ 138.791000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 138.791000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns * has 3 failures:
0.chip_sw_soc_proxy_gpios.26591530226508352749075373495197114031707865553200684799670259469492239578035
Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log
UVM_ERROR @ 136.478000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
UVM_INFO @ 136.478000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_gpios.36422348088651144595226633504431101498804669104236466812296091277322892519935
Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_gpios/latest/run.log
UVM_ERROR @ 136.450000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/tests/soc_proxy_gpios.c:35)] DIF-fail: dif_pinmux_input_select(&pinmux, peripheral_in[i], insel[i]) returns 9
UVM_INFO @ 136.450000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 3 failures:
0.chip_sw_aon_timer_irq.17912874208859774723243786014757774149322822173812883490967708743615546528941
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
UVM_ERROR @ 602.553000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4637 usec which is not in the range 423 usec and 482 usec
UVM_INFO @ 602.553000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aon_timer_irq.70366153433144004624121328101523037846831317730232847109289544348654357785244
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log
UVM_ERROR @ 588.529000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4492 usec which is not in the range 410 usec and 467 usec
UVM_INFO @ 588.529000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:
0.chip_sw_aon_timer_wdog_bite_reset.14369553051755887005718741576110803056897106826028696344258086780115726658115
Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
UVM_ERROR @ 164.317000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 164.317000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aon_timer_wdog_bite_reset.34982867956095574067369425429725958716383145943243868715918482034308701403508
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
UVM_ERROR @ 164.340000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 164.340000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
0.chip_sw_rv_core_ibex_nmi_irq.85414557457573496694222928817175404325457382414860835193588599843556564833236
Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
UVM_ERROR @ 251.622000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 251.622000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_core_ibex_nmi_irq.42624719735254845226041140964500593340964062774447751208355135467913982884968
Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
UVM_ERROR @ 251.546000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 251.546000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
0.chip_sw_kmac_app_rom.38599649612406765913047936254833602376370703394680628866240892106182603989371
Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_kmac_app_rom.114848669523455291913240022982224694430708037297567383713436110507598397966149
Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 3 failures:
2.chip_sw_all_escalation_resets.45322536227586495954091206792269000807729460349219402926913340145465743628695
Line 417, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log
UVM_FATAL @ 10.400001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
58.chip_sw_all_escalation_resets.45873094369674507530820296249743706551129570349661132826477384653016537232656
Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest/run.log
UVM_FATAL @ 10.300001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
17.chip_sw_all_escalation_resets.72254286557100629746494630542383929582180564934992837225996578344969898753933
Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 158.720000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
UVM_INFO @ 158.720000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.chip_sw_all_escalation_resets.70986696233929196008675323956896177783971261496564337942092253556368880618590
Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 158.710000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
UVM_INFO @ 158.710000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 2 failures:
6.chip_sw_all_escalation_resets.9383557012165898268996810720250083210920582585254110470387855349812627054151
Line 437, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 160.172000 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 160.172000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.chip_sw_all_escalation_resets.115267413042474084812262947142621438521755573836821042704290750254396694235898
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 162.240000 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 162.240000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31487) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.chip_tl_errors.101278250914258271281344474134627533265110258279061716066764230570792222259891
Line 228, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_tl_errors/latest/run.log
UVM_ERROR @ 117.971000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31487) { a_addr: 'h40544 a_data: 'hb7d9e0a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7 a_opcode: 'h4 a_user: 'h1919a d_param: 'h0 d_source: 'h7 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.971000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33199) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
6.chip_tl_errors.114500706437080873619439510407278520082533205239173699978392372452600245381909
Line 228, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_tl_errors/latest/run.log
UVM_ERROR @ 118.302000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33199) { a_addr: 'h40610 a_data: 'h1a9641e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h19d0b d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 118.302000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32545) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
11.chip_tl_errors.6681461509857316811569331021678366871070737576655891891292566066852196329314
Line 228, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/11.chip_tl_errors/latest/run.log
UVM_ERROR @ 118.194000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32545) { a_addr: 'h40700 a_data: 'h4fc8a5fd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1a a_opcode: 'h4 a_user: 'h1beb9 d_param: 'h0 d_source: 'h1a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 118.194000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31663) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
21.chip_tl_errors.69810021662962872071141295523423735398901163515297011080983424246584021532067
Line 228, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_tl_errors/latest/run.log
UVM_ERROR @ 118.067000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31663) { a_addr: 'h40670 a_data: 'h926f3679 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h1ad52 d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 118.067000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! has 1 failures:
0.chip_sw_soc_proxy_smoketest.98957226109203695273196269302302990226363255261505025661799782505786907145662
Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
UVM_ERROR @ 137.296000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
UVM_INFO @ 137.296000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@48874) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.chip_sw_rv_core_ibex_lockstep_glitch.28410471639658174170466067361714689846448389922496565330478549054526400104850
Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_ERROR @ 136.952000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@48874) { a_addr: 'h41102bd8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h4 a_user: 'h2482a d_param: 'h0 d_source: 'h1 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 136.952000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * has 1 failures:
0.chip_sw_dma_abort.51578578069297766581002803042083248588381305116647528729315532529697363631870
Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
UVM_ERROR @ 192.882000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
UVM_INFO @ 192.882000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
1.chip_sw_dma_abort.54090898843519404652109809403476453864556992864889230526145874834788936299690
Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log
UVM_FATAL @ 173.752000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
UVM_INFO @ 173.752000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== has 1 failures:
2.chip_sw_dma_abort.35641122235023905343424369134370133108155113257916923746609725993646832109737
Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_abort/latest/run.log
UVM_ERROR @ 184.544000 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
UVM_INFO @ 184.544000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---