Simulation Results: ac_range_check

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.28 %
  • code
  • 93.54 %
  • assert
  • 97.63 %
  • func
  • 58.67 %
  • block
  • 99.21 %
  • line
  • 99.94 %
  • branch
  • 98.35 %
  • toggle
  • 82.34 %
Validation stages
V1
96.67%
V2
98.71%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 18 20 90.00
ac_range_check_smoke 52.000s 2333.569us 18 20 90.00
ac_range_check_smoke_racl 18 20 90.00
ac_range_check_smoke_racl 85.000s 8585.502us 18 20 90.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 3.000s 111.286us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 4.000s 196.272us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 55.000s 1704.244us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 33.000s 9310.783us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 100.309us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 4.000s 196.272us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 9310.783us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 212.226us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 42.000s 1166.784us 1 1 100.00
stress_all 46 50 92.00
ac_range_check_stress_all 368.000s 8375.549us 46 50 92.00
alert_test 50 50 100.00
ac_range_check_alert_test 3.000s 46.972us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 2.000s 14.754us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 6.000s 431.034us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 6.000s 431.034us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 111.286us 5 5 100.00
ac_range_check_csr_rw 4.000s 196.272us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 9310.783us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 396.978us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 111.286us 5 5 100.00
ac_range_check_csr_rw 4.000s 196.272us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 9310.783us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 396.978us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 29.000s 1114.448us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 29.000s 1114.448us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 29.000s 1114.448us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 29.000s 1114.448us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 144.000s 5277.825us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 2.000s 12.317us 5 5 100.00
ac_range_check_tl_intg_err 18.000s 403.019us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 408.000s 61664.022us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 52.000s 5817.833us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_stress_all 4951512052384316896470891355781425713441210108546229063529874336227881468729 8851
UVM_ERROR @ 3695079314 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 3695079314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 109890581694724283676567767685658380322672291496210406293506999994646164698848 3981
UVM_ERROR @ 1196856798 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1196856798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 7376601391452020192797351634513586627751298997529069068773450493606851331119 4781
UVM_ERROR @ 2377594045 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2377594045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 6600876080265779216617243128116229384048800925071406569216785940053477287984 4823
UVM_ERROR @ 994009706 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 994009706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 100567617674263132897945732990610060731067828304265379830783335694314534907826 4723
UVM_ERROR @ 8585501777 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 8585501777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 26444682583318023620886334432178156812142535409129713740744245843654835332584 4764
UVM_ERROR @ 4556928838 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 4556928838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 92503888151152277932901000487821716273490855791040755270464621144033130258621 4218
UVM_ERROR @ 6647485982 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 6647485982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 12788360610886853341185667508679209969928790119520334707212977056590381392476 18361
UVM_ERROR @ 2048808131 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2048808131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---