| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| aon_timer_smoke | 1.700s | 610.049us | 5 | 5 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.820s | 1107.341us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| aon_timer_csr_rw | 1.810s | 402.058us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| aon_timer_csr_bit_bash | 8.620s | 12475.769us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| aon_timer_csr_aliasing | 1.790s | 578.109us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 1.670s | 484.507us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| aon_timer_csr_rw | 1.810s | 402.058us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 1.790s | 578.109us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| aon_timer_mem_walk | 1.200s | 392.100us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| aon_timer_mem_partial_access | 1.640s | 434.205us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 15 | 15 | 100.00 | |||
| aon_timer_prescaler | 78.800s | 58233.122us | 15 | 15 | 100.00 | |
| jump | 5 | 5 | 100.00 | |||
| aon_timer_jump | 2.360s | 709.791us | 5 | 5 | 100.00 | |
| stress_all | 15 | 15 | 100.00 | |||
| aon_timer_stress_all | 228.010s | 159704.092us | 15 | 15 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| aon_timer_alert_test | 2.080s | 493.263us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| aon_timer_intr_test | 1.710s | 378.341us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| aon_timer_tl_errors | 3.040s | 569.770us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| aon_timer_tl_errors | 3.040s | 569.770us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.820s | 1107.341us | 5 | 5 | 100.00 | |
| aon_timer_csr_rw | 1.810s | 402.058us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 1.790s | 578.109us | 5 | 5 | 100.00 | |
| aon_timer_same_csr_outstanding | 6.350s | 2036.168us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.820s | 1107.341us | 5 | 5 | 100.00 | |
| aon_timer_csr_rw | 1.810s | 402.058us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 1.790s | 578.109us | 5 | 5 | 100.00 | |
| aon_timer_same_csr_outstanding | 6.350s | 2036.168us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| aon_timer_sec_cm | 12.980s | 8352.688us | 5 | 5 | 100.00 | |
| aon_timer_tl_intg_err | 11.450s | 8198.922us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| aon_timer_tl_intg_err | 11.450s | 8198.922us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_max_thold | 2.130s | 643.809us | 5 | 5 | 100.00 | |
| min_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_min_thold | 2.440s | 674.315us | 5 | 5 | 100.00 | |
| wkup_count_hi_cdc | 5 | 5 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 10.410s | 3487.190us | 5 | 5 | 100.00 | |
| custom_intr | 10 | 10 | 100.00 | |||
| aon_timer_custom_intr | 2.100s | 635.493us | 10 | 10 | 100.00 | |
| alternating_on_off | 5 | 5 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 7.670s | 3941.252us | 5 | 5 | 100.00 | |
| stress_all_with_rand_reset | 15 | 15 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 31.010s | 15988.056us | 15 | 15 | 100.00 | |
| Test | seed | line | log context |
|---|