Simulation Results: csrng

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.47 %
  • code
  • 96.35 %
  • assert
  • 95.85 %
  • func
  • 91.21 %
  • block
  • 98.76 %
  • line
  • 99.64 %
  • branch
  • 96.88 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.94%
V2S
99.98%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 4.000s 125.405us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 3.000s 92.665us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 3.000s 34.325us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 21.000s 1528.250us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 8.000s 594.969us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 5.000s 362.723us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 3.000s 34.325us 20 20 100.00
csrng_csr_aliasing 8.000s 594.969us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
alerts 500 500 100.00
csrng_alert 33.000s 2774.704us 500 500 100.00
err 500 500 100.00
csrng_err 8.000s 38.781us 500 500 100.00
cmds 50 50 100.00
csrng_cmds 376.000s 29509.709us 50 50 100.00
life cycle 50 50 100.00
csrng_cmds 376.000s 29509.709us 50 50 100.00
stress_all 49 50 98.00
csrng_stress_all 1153.000s 107301.065us 49 50 98.00
intr_test 50 50 100.00
csrng_intr_test 3.000s 64.295us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 4.000s 78.631us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 22.000s 1952.474us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 22.000s 1952.474us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 3.000s 92.665us 5 5 100.00
csrng_csr_rw 3.000s 34.325us 20 20 100.00
csrng_csr_aliasing 8.000s 594.969us 5 5 100.00
csrng_same_csr_outstanding 4.000s 207.088us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 3.000s 92.665us 5 5 100.00
csrng_csr_rw 3.000s 34.325us 20 20 100.00
csrng_csr_aliasing 8.000s 594.969us 5 5 100.00
csrng_same_csr_outstanding 4.000s 207.088us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_tl_intg_err 11.000s 723.788us 20 20 100.00
csrng_sec_cm 5.000s 325.218us 5 5 100.00
sec_cm_config_regwen 70 70 100.00
csrng_csr_rw 3.000s 34.325us 20 20 100.00
csrng_regwen 3.000s 116.857us 50 50 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 33.000s 2774.704us 500 500 100.00
sec_cm_intersig_mubi 49 50 98.00
csrng_stress_all 1153.000s 107301.065us 49 50 98.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
csrng_err 8.000s 38.781us 500 500 100.00
csrng_sec_cm 5.000s 325.218us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
csrng_err 8.000s 38.781us 500 500 100.00
csrng_sec_cm 5.000s 325.218us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
csrng_err 8.000s 38.781us 500 500 100.00
csrng_sec_cm 5.000s 325.218us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
csrng_err 8.000s 38.781us 500 500 100.00
csrng_sec_cm 5.000s 325.218us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
csrng_err 8.000s 38.781us 500 500 100.00
csrng_sec_cm 5.000s 325.218us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 33.000s 2774.704us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
csrng_err 8.000s 38.781us 500 500 100.00
sec_cm_constants_lc_gated 49 50 98.00
csrng_stress_all 1153.000s 107301.065us 49 50 98.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 33.000s 2774.704us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 11.000s 723.788us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
csrng_err 8.000s 38.781us 500 500 100.00
csrng_sec_cm 5.000s 325.218us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
csrng_err 8.000s 38.781us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
csrng_err 8.000s 38.781us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
csrng_err 8.000s 38.781us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
csrng_err 8.000s 38.781us 500 500 100.00
csrng_sec_cm 5.000s 325.218us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 18.000s 1047.567us 200 200 100.00
csrng_err 8.000s 38.781us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
csrng_stress_all_with_rand_reset 293.000s 18676.829us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
csrng_stress_all 488243603835667646691378784074274585339691396540304202621199348377501841934 145
UVM_ERROR @ 102007925 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 102007925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---