Simulation Results: dma

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.27 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 76.65 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 10.000s 347.951us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 9.000s 1453.148us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 10.000s 1376.648us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 74.342us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 216.898us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 14.000s 1508.338us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 7.000s 587.167us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 167.216us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 216.898us 20 20 100.00
dma_csr_aliasing 7.000s 587.167us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 189.000s 73696.809us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 472.000s 42338.701us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 600.000s 144348.674us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 600.000s 144348.674us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 472.000s 42338.701us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 268.000s 76646.201us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 600.000s 144348.674us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 14.000s 757.764us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 364.000s 74623.454us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 28.703us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 6.000s 26.400us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 3.000s 322.319us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 3.000s 322.319us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 74.342us 5 5 100.00
dma_csr_rw 2.000s 216.898us 20 20 100.00
dma_csr_aliasing 7.000s 587.167us 5 5 100.00
dma_same_csr_outstanding 3.000s 195.372us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 74.342us 5 5 100.00
dma_csr_rw 2.000s 216.898us 20 20 100.00
dma_csr_aliasing 7.000s 587.167us 5 5 100.00
dma_same_csr_outstanding 3.000s 195.372us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 26.000s 337.788us 5 5 100.00
dma_generic_stress 268.000s 76646.201us 5 5 100.00
dma_handshake_stress 600.000s 144348.674us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 12.000s 1170.354us 15 15 100.00
tl_intg_err 25 25 100.00
dma_sec_cm 2.000s 36.963us 5 5 100.00
dma_tl_intg_err 5.000s 424.954us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 157.000s 56512.925us 25 25 100.00
dma_longer_transfer 30.000s 4335.001us 5 5 100.00
dma_stress_all_with_rand_reset 12.000s 523.127us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 54316856796216626801141805772294416713774146513484240245766036135265014852689 100
UVM_ERROR @ 523127490ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 523127490ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---