Simulation Results: hmac

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.78 %
  • code
  • 98.72 %
  • assert
  • 97.61 %
  • func
  • 100.00 %
  • line
  • 99.95 %
  • branch
  • 99.83 %
  • cond
  • 96.74 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 17.460s 2024.841us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.320s 218.098us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.230s 16.847us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 15.960s 1048.016us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 7.460s 452.637us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 225.850s 132787.297us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.230s 16.847us 20 20 100.00
hmac_csr_aliasing 7.460s 452.637us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 119.520s 6900.577us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 125.350s 1945.579us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 276.980s 14656.173us 30 30 100.00
hmac_test_sha384_vectors 523.160s 52976.599us 75 75 100.00
hmac_test_sha512_vectors 549.740s 55470.070us 75 75 100.00
hmac_test_hmac256_vectors 14.420s 653.739us 50 50 100.00
hmac_test_hmac384_vectors 18.360s 787.016us 60 60 100.00
hmac_test_hmac512_vectors 19.980s 1529.720us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 47.990s 31371.677us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1025.650s 6524.038us 10 10 100.00
error 10 10 100.00
hmac_error 102.730s 24610.584us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 112.230s 8518.960us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 17.460s 2024.841us 10 10 100.00
hmac_long_msg 119.520s 6900.577us 10 10 100.00
hmac_back_pressure 125.350s 1945.579us 25 25 100.00
hmac_datapath_stress 1025.650s 6524.038us 10 10 100.00
hmac_burst_wr 47.990s 31371.677us 50 50 100.00
hmac_stress_all 1643.780s 318640.879us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 17.460s 2024.841us 10 10 100.00
hmac_long_msg 119.520s 6900.577us 10 10 100.00
hmac_back_pressure 125.350s 1945.579us 25 25 100.00
hmac_datapath_stress 1025.650s 6524.038us 10 10 100.00
hmac_wipe_secret 112.230s 8518.960us 10 10 100.00
hmac_test_sha256_vectors 276.980s 14656.173us 30 30 100.00
hmac_test_sha384_vectors 523.160s 52976.599us 75 75 100.00
hmac_test_sha512_vectors 549.740s 55470.070us 75 75 100.00
hmac_test_hmac256_vectors 14.420s 653.739us 50 50 100.00
hmac_test_hmac384_vectors 18.360s 787.016us 60 60 100.00
hmac_test_hmac512_vectors 19.980s 1529.720us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 17.460s 2024.841us 10 10 100.00
hmac_long_msg 119.520s 6900.577us 10 10 100.00
hmac_back_pressure 125.350s 1945.579us 25 25 100.00
hmac_datapath_stress 1025.650s 6524.038us 10 10 100.00
hmac_burst_wr 47.990s 31371.677us 50 50 100.00
hmac_error 102.730s 24610.584us 10 10 100.00
hmac_wipe_secret 112.230s 8518.960us 10 10 100.00
hmac_test_sha256_vectors 276.980s 14656.173us 30 30 100.00
hmac_test_sha384_vectors 523.160s 52976.599us 75 75 100.00
hmac_test_sha512_vectors 549.740s 55470.070us 75 75 100.00
hmac_test_hmac256_vectors 14.420s 653.739us 50 50 100.00
hmac_test_hmac384_vectors 18.360s 787.016us 60 60 100.00
hmac_test_hmac512_vectors 19.980s 1529.720us 75 75 100.00
hmac_stress_all 1643.780s 318640.879us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1643.780s 318640.879us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.920s 13.530us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.940s 37.029us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.300s 199.373us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.300s 199.373us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.320s 218.098us 5 5 100.00
hmac_csr_rw 1.230s 16.847us 20 20 100.00
hmac_csr_aliasing 7.460s 452.637us 5 5 100.00
hmac_same_csr_outstanding 2.790s 154.038us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.320s 218.098us 5 5 100.00
hmac_csr_rw 1.230s 16.847us 20 20 100.00
hmac_csr_aliasing 7.460s 452.637us 5 5 100.00
hmac_same_csr_outstanding 2.790s 154.038us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.360s 65.074us 5 5 100.00
hmac_tl_intg_err 5.190s 2538.887us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 5.190s 2538.887us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 17.460s 2024.841us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.980s 129.150us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 496.510s 48780.400us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.460s 480.792us 1 1 100.00

Error Messages

   Test seed line log context