keymgr Simulation Results

Simulation Results: keymgr

12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.94 %

code
98.97 %

assert
97.72 %

func
91.13 %

line
99.13 %

branch
99.01 %

cond
98.11 %

toggle
98.61 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.05%
V2S		99.61%
V3		52.00%

180/180 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	keymgr_smoke	16.800s	5847.598us	50	50	100.00
random				50	50	100.00
	keymgr_random	57.140s	3802.087us	50	50	100.00
csr_hw_reset				5	5	100.00
	keymgr_csr_hw_reset	1.470s	18.010us	5	5	100.00
csr_rw				20	20	100.00
	keymgr_csr_rw	1.650s	173.610us	20	20	100.00
csr_bit_bash				5	5	100.00
	keymgr_csr_bit_bash	24.560s	2166.577us	5	5	100.00
csr_aliasing				5	5	100.00
	keymgr_csr_aliasing	7.580s	533.243us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	keymgr_csr_mem_rw_with_rand_reset	2.310s	260.891us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	keymgr_csr_rw	1.650s	173.610us	20	20	100.00
	keymgr_csr_aliasing	7.580s	533.243us	5	5	100.00

832/840 passed

99.05 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
cfgen_during_op				50	50	100.00
	keymgr_cfg_regwen	59.410s	1693.915us	50	50	100.00
sideload				199	200	99.50
	keymgr_sideload	54.050s	16665.709us	50	50	100.00
	keymgr_sideload_kmac	35.270s	5970.319us	50	50	100.00
	keymgr_sideload_aes	53.900s	8113.715us	49	50	98.00
	keymgr_sideload_otbn	37.320s	1327.245us	50	50	100.00
direct_to_disabled_state				50	50	100.00
	keymgr_direct_to_disabled	26.820s	3616.489us	50	50	100.00
lc_disable				48	50	96.00
	keymgr_lc_disable	14.770s	327.147us	48	50	96.00
kmac_error_response				50	50	100.00
	keymgr_kmac_rsp_err	11.760s	2678.835us	50	50	100.00
invalid_sw_input				50	50	100.00
	keymgr_sw_invalid_input	35.310s	6764.689us	50	50	100.00
invalid_hw_input				50	50	100.00
	keymgr_hwsw_invalid_input	15.520s	732.376us	50	50	100.00
sync_async_fault_cross				49	50	98.00
	keymgr_sync_async_fault_cross	7.520s	911.784us	49	50	98.00
stress_all				46	50	92.00
	keymgr_stress_all	346.770s	273022.310us	46	50	92.00
intr_test				50	50	100.00
	keymgr_intr_test	1.140s	41.404us	50	50	100.00
alert_test				50	50	100.00
	keymgr_alert_test	1.320s	21.544us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	keymgr_tl_errors	4.300s	138.591us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	keymgr_tl_errors	4.300s	138.591us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	keymgr_csr_hw_reset	1.470s	18.010us	5	5	100.00
	keymgr_csr_rw	1.650s	173.610us	20	20	100.00
	keymgr_csr_aliasing	7.580s	533.243us	5	5	100.00
	keymgr_same_csr_outstanding	3.440s	217.564us	20	20	100.00
tl_d_partial_access				50	50	100.00
	keymgr_csr_hw_reset	1.470s	18.010us	5	5	100.00
	keymgr_csr_rw	1.650s	173.610us	20	20	100.00
	keymgr_csr_aliasing	7.580s	533.243us	5	5	100.00
	keymgr_same_csr_outstanding	3.440s	217.564us	20	20	100.00

V2S

1026/1030 passed

99.61 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				5	5	100.00
	keymgr_sec_cm	19.110s	1090.980us	5	5	100.00
tl_intg_err				25	25	100.00
	keymgr_sec_cm	19.110s	1090.980us	5	5	100.00
	keymgr_tl_intg_err	7.040s	239.635us	20	20	100.00
shadow_reg_update_error				20	20	100.00
	keymgr_shadow_reg_errors	4.710s	1401.556us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	keymgr_shadow_reg_errors	4.710s	1401.556us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	keymgr_shadow_reg_errors	4.710s	1401.556us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	keymgr_shadow_reg_errors	4.710s	1401.556us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	keymgr_shadow_reg_errors_with_csr_rw	15.230s	5239.580us	20	20	100.00
prim_count_check				5	5	100.00
	keymgr_sec_cm	19.110s	1090.980us	5	5	100.00
prim_fsm_check				5	5	100.00
	keymgr_sec_cm	19.110s	1090.980us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	keymgr_tl_intg_err	7.040s	239.635us	20	20	100.00
sec_cm_config_shadow				20	20	100.00
	keymgr_shadow_reg_errors	4.710s	1401.556us	20	20	100.00
sec_cm_op_config_regwen				50	50	100.00
	keymgr_cfg_regwen	59.410s	1693.915us	50	50	100.00
sec_cm_reseed_config_regwen				70	70	100.00
	keymgr_random	57.140s	3802.087us	50	50	100.00
	keymgr_csr_rw	1.650s	173.610us	20	20	100.00
sec_cm_sw_binding_config_regwen				70	70	100.00
	keymgr_random	57.140s	3802.087us	50	50	100.00
	keymgr_csr_rw	1.650s	173.610us	20	20	100.00
sec_cm_max_key_ver_config_regwen				70	70	100.00
	keymgr_random	57.140s	3802.087us	50	50	100.00
	keymgr_csr_rw	1.650s	173.610us	20	20	100.00
sec_cm_lc_ctrl_intersig_mubi				48	50	96.00
	keymgr_lc_disable	14.770s	327.147us	48	50	96.00
sec_cm_constants_consistency				50	50	100.00
	keymgr_hwsw_invalid_input	15.520s	732.376us	50	50	100.00
sec_cm_intersig_consistency				50	50	100.00
	keymgr_hwsw_invalid_input	15.520s	732.376us	50	50	100.00
sec_cm_hw_key_sw_noaccess				50	50	100.00
	keymgr_random	57.140s	3802.087us	50	50	100.00
sec_cm_output_keys_ctrl_redun				50	50	100.00
	keymgr_sideload_protect	15.380s	751.845us	50	50	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	19.110s	1090.980us	5	5	100.00
sec_cm_data_fsm_sparse				5	5	100.00
	keymgr_sec_cm	19.110s	1090.980us	5	5	100.00
sec_cm_ctrl_fsm_local_esc				5	5	100.00
	keymgr_sec_cm	19.110s	1090.980us	5	5	100.00
sec_cm_ctrl_fsm_consistency				50	50	100.00
	keymgr_custom_cm	17.700s	545.161us	50	50	100.00
sec_cm_ctrl_fsm_global_esc				48	50	96.00
	keymgr_lc_disable	14.770s	327.147us	48	50	96.00
sec_cm_ctrl_ctr_redun				5	5	100.00
	keymgr_sec_cm	19.110s	1090.980us	5	5	100.00
sec_cm_kmac_if_fsm_sparse				5	5	100.00
	keymgr_sec_cm	19.110s	1090.980us	5	5	100.00
sec_cm_kmac_if_ctr_redun				5	5	100.00
	keymgr_sec_cm	19.110s	1090.980us	5	5	100.00
sec_cm_kmac_if_cmd_ctrl_consistency				50	50	100.00
	keymgr_custom_cm	17.700s	545.161us	50	50	100.00
sec_cm_kmac_if_done_ctrl_consistency				50	50	100.00
	keymgr_custom_cm	17.700s	545.161us	50	50	100.00
sec_cm_reseed_ctr_redun				5	5	100.00
	keymgr_sec_cm	19.110s	1090.980us	5	5	100.00
sec_cm_side_load_sel_ctrl_consistency				50	50	100.00
	keymgr_custom_cm	17.700s	545.161us	50	50	100.00
sec_cm_sideload_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	19.110s	1090.980us	5	5	100.00
sec_cm_ctrl_key_integrity				50	50	100.00
	keymgr_custom_cm	17.700s	545.161us	50	50	100.00

26/50 passed

52.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				26	50	52.00
	keymgr_stress_all_with_rand_reset	20.420s	2752.791us	26	50	52.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	keymgr_stress_all_with_rand_reset	6308384267900676912978000177982541995558890818416038504500312763376428558468	183	UVM_ERROR @ 677692962 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 677692962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	106004584924228014339627480096776371600185855566248981475540830389383932177964	1227	UVM_ERROR @ 466423216 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 466423216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	108784683021639681667095379895068574686213550085666136303088831963212974566707	1107	UVM_ERROR @ 549464635 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 549464635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	45337583026724784112076660491916561041824348504111340134510832355750407094530	218	UVM_ERROR @ 159903563 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 159903563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	19794344866822156008862701731687993558960518001589776077317109409812642170142	1335	UVM_ERROR @ 1106247999 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1106247999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	36072464032566913976945829860654248521799637612169642508942815044251305655779	93	UVM_ERROR @ 103294762 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 103294762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	63312614831513678583906593085737263852967985911083531430245065652850056292332	145	UVM_ERROR @ 289266356 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 289266356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	95361626612829276941141877975931792101948300697530640915144504124882985244170	435	UVM_ERROR @ 144289742 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 144289742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	65566376745317194257240242654569796499613669170615473261476215806671211175508	94	UVM_ERROR @ 177578079 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 177578079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	18367884072306804401309753868577364356931219733866348404687372319609018258730	948	UVM_ERROR @ 854821701 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 854821701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	36448843608606719260001648949815572276287983087856628104901414195777471676238	145	UVM_ERROR @ 238677678 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 238677678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	75942973961195154600634934128746409490374007126665738622060757504092290637132	913	UVM_ERROR @ 249789374 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 249789374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	53749751136545198568334625396953767214246393841394504467292899732434909313269	620	UVM_ERROR @ 288007227 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 288007227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	5158019695668850831227830387270448961790183514987386176887393743257820954758	1012	UVM_ERROR @ 577231386 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 577231386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	80172230673478450698657706918571686044037476011671297896620565097785193046844	134	UVM_ERROR @ 499023643 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 499023643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	93602761484773678281264981550086814359534131382176084141119792835778663500214	140	UVM_ERROR @ 119421699 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 119421699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	71394096122022420192420885598751955929092855413505277798576196730852896031911	129	UVM_ERROR @ 107059873 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 107059873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	9774971817973301928241200675196029424658971698694537003797441282309107320745	94	UVM_ERROR @ 235285403 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 235285403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	30666942307279928877426411240109879558570088678911417937359754370298635623462	181	UVM_ERROR @ 106305547 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 106305547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	40099346180804711875951004725310997558149403311524000188154702317273316433733	399	UVM_ERROR @ 561518385 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 561518385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	495283142155734802118758040693531680533196276539104014412093478789951745084	134	UVM_ERROR @ 621893848 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 621893848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	37417042408608858629066450158046168356988988787098877289526659307368526841114	637	UVM_ERROR @ 788677748 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 788677748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	18391957667342996174436292538411806004476310995850948159555950160139106526882	145	UVM_ERROR @ 476993867 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 476993867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	38972538356172515067539327948093300812671200181488993347506683671487065195343	239	UVM_ERROR @ 119414128 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 119414128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [] vs []) reg name: keymgr_reg_block.sw_share1_output_
	keymgr_lc_disable	41098558004961480817230697446884655664733596370117801307655589955698919280658	204	UVM_ERROR @ 209733701 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_5 UVM_INFO @ 209733701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all	108629164478418119794491657971904002134662291510488369884332328064206620702740	1374	UVM_ERROR @ 994284964 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_5 UVM_INFO @ 994284964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
	keymgr_sideload_aes	42735865486040091096185274446668057162687252154224885172306875410038222977650	108	UVM_ERROR @ 19938357 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4 UVM_INFO @ 19938357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_lc_disable	84926015447935641509571307485692728060425281413298225888750152586855225636365	91	UVM_ERROR @ 41136743 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000 UVM_INFO @ 41136743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all	6243510184587567471592348691017690358283487270707417632350048617825315990407	1607	UVM_ERROR @ 305502439 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4 UVM_INFO @ 305502439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received!
	keymgr_sync_async_fault_cross	11409320752005225730363126802862214611871673495656892244591160809618421409550	211	UVM_ERROR @ 42444416 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received! UVM_INFO @ 42444416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[], act_key.key[]} !== keys_a_array[state][cdi][dest] (* [] vs [*]) AES key at state StOwnerIntKey for Attestation Aes
	keymgr_stress_all	77643807910304888747330862057802033710465729927349431759541098856092322106425	554	UVM_ERROR @ 743791210 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (5530745184056751682630366527552010553793346744544937166596332046935195521154094026706731152301555384311039309009036028617644010859571986005603319150337678 [0x6999b825e1e8da46627ac52d7f637a90defcdd37602a6f9526981622eed9e52c3ad436aec33c8f902ee27232bee4d0b2dd28618b23b55220d95c7459f88cde8e] vs 5530745184056751682630366527552010553793346744544937166596332046935195521154094026706731152301555384311039309009036028617644010859571986005603319150337678 [0x6999b825e1e8da46627ac52d7f637a90defcdd37602a6f9526981622eed9e52c3ad436aec33c8f902ee27232bee4d0b2dd28618b23b55220d95c7459f88cde8e]) AES key at state StOwnerIntKey for Attestation Aes UVM_INFO @ 743791210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [] vs []) reg name: keymgr_reg_block.sw_share0_output_
	keymgr_stress_all	96936938604572330496899638051732642213270973527753893960795390012419036213900	3462	UVM_ERROR @ 5445423210 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_3 UVM_INFO @ 5445423210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---