Simulation Results: keymgr_dpe

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.38 %
  • code
  • 84.26 %
  • assert
  • 97.64 %
  • func
  • 17.25 %
  • line
  • 97.62 %
  • branch
  • 94.61 %
  • cond
  • 90.26 %
  • toggle
  • 63.15 %
  • FSM
  • 75.68 %
Validation stages
V1
99.23%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_dpe_smoke 193.750s 34606.267us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_dpe_csr_hw_reset 1.460s 103.617us 5 5 100.00
csr_rw 20 20 100.00
keymgr_dpe_csr_rw 1.340s 44.718us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_dpe_csr_bit_bash 8.750s 1862.680us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_dpe_csr_aliasing 5.440s 1054.999us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.700s 46.572us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_dpe_csr_rw 1.340s 44.718us 20 20 100.00
keymgr_dpe_csr_aliasing 5.440s 1054.999us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 50 50 100.00
keymgr_dpe_intr_test 1.160s 9.121us 50 50 100.00
alert_test 50 50 100.00
keymgr_dpe_alert_test 1.300s 21.290us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_dpe_tl_errors 4.280s 1734.253us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_dpe_tl_errors 4.280s 1734.253us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_dpe_csr_hw_reset 1.460s 103.617us 5 5 100.00
keymgr_dpe_csr_rw 1.340s 44.718us 20 20 100.00
keymgr_dpe_csr_aliasing 5.440s 1054.999us 5 5 100.00
keymgr_dpe_same_csr_outstanding 2.250s 223.100us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_dpe_csr_hw_reset 1.460s 103.617us 5 5 100.00
keymgr_dpe_csr_rw 1.340s 44.718us 20 20 100.00
keymgr_dpe_csr_aliasing 5.440s 1054.999us 5 5 100.00
keymgr_dpe_same_csr_outstanding 2.250s 223.100us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
keymgr_dpe_sec_cm 14.920s 739.411us 5 5 100.00
keymgr_dpe_tl_intg_err 6.430s 463.436us 20 20 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 2.840s 675.187us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 2.840s 675.187us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 2.840s 675.187us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 2.840s 675.187us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 6.900s 351.139us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 14.920s 739.411us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 14.920s 739.411us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.debug reset value: *
keymgr_dpe_csr_mem_rw_with_rand_reset 56139001650235381155006933958263301457001137873631005359213672416675125663658 94
UVM_ERROR @ 36770567 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (256 [0x100] vs 0 [0x0]) Regname: keymgr_dpe_reg_block.debug reset value: 0x0
UVM_INFO @ 36770567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---