Simulation Results: kmac

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.54 %
  • code
  • 93.93 %
  • assert
  • 97.83 %
  • func
  • 97.86 %
  • line
  • 99.27 %
  • branch
  • 97.15 %
  • cond
  • 94.45 %
  • toggle
  • 99.89 %
  • FSM
  • 78.87 %
Validation stages
V1
100.00%
V2
99.64%
V2S
99.80%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 87.870s 8042.131us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 0.940s 29.567us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.040s 55.269us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 13.130s 1458.477us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.930s 2093.905us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 1.970s 132.116us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.040s 55.269us 20 20 100.00
kmac_csr_aliasing 6.930s 2093.905us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.750s 22.157us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.370s 150.711us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3529.240s 135590.068us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1322.020s 29040.318us 50 50 100.00
test_vectors 39 40 97.50
kmac_test_vectors_sha3_224 2221.500s 388656.544us 4 5 80.00
kmac_test_vectors_sha3_256 1539.130s 238666.547us 5 5 100.00
kmac_test_vectors_sha3_384 1424.280s 222594.414us 5 5 100.00
kmac_test_vectors_sha3_512 1342.100s 184467.617us 5 5 100.00
kmac_test_vectors_shake_128 1756.300s 143065.038us 5 5 100.00
kmac_test_vectors_shake_256 2115.660s 956744.958us 5 5 100.00
kmac_test_vectors_kmac 4.070s 189.182us 5 5 100.00
kmac_test_vectors_kmac_xof 3.410s 743.065us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 460.510s 20042.604us 50 50 100.00
app 50 50 100.00
kmac_app 322.920s 205489.735us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 362.120s 45897.042us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 338.050s 37000.313us 50 50 100.00
error 50 50 100.00
kmac_error 434.360s 52926.500us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 23.230s 21707.757us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 8.710s 1190.596us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 39.720s 7766.580us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 42.050s 2241.312us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 72.610s 26713.801us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 29.890s 1881.220us 50 50 100.00
stress_all 48 50 96.00
kmac_stress_all 2358.830s 71717.512us 48 50 96.00
intr_test 50 50 100.00
kmac_intr_test 0.830s 35.753us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.280s 134.011us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.060s 204.633us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.060s 204.633us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 0.940s 29.567us 5 5 100.00
kmac_csr_rw 1.040s 55.269us 20 20 100.00
kmac_csr_aliasing 6.930s 2093.905us 5 5 100.00
kmac_same_csr_outstanding 2.000s 223.110us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 0.940s 29.567us 5 5 100.00
kmac_csr_rw 1.040s 55.269us 20 20 100.00
kmac_csr_aliasing 6.930s 2093.905us 5 5 100.00
kmac_same_csr_outstanding 2.000s 223.110us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 1.690s 82.915us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 1.690s 82.915us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 1.690s 82.915us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 1.690s 82.915us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 3.660s 230.498us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 3.440s 454.613us 20 20 100.00
kmac_sec_cm 137.500s 73230.737us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 3.440s 454.613us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 29.890s 1881.220us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 87.870s 8042.131us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 460.510s 20042.604us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 1.690s 82.915us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 137.500s 73230.737us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 137.500s 73230.737us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 137.500s 73230.737us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 87.870s 8042.131us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 29.890s 1881.220us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 137.500s 73230.737us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 326.980s 13027.394us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 87.870s 8042.131us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 139.950s 26886.689us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 72951182664390356758351902506096889765330928030209745172523594914834554593685 416
UVM_ERROR @ 115958469 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2288808027 [0x886c705b] vs 0 [0x0]) Regname: kmac_reg_block.prefix_7.prefix_0 reset value: 0x0
UVM_INFO @ 115958469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_test_vectors_sha3_224 44867293075021767187425957716179849386734043457299418214365938646513707483689 75
UVM_ERROR @ 35100816 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 35100816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 26111827469076120333513774118216154666419536093802598219543303156288927386595 163
UVM_ERROR @ 8562427745 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 8562427745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 43203352757437682302907700974601002166722495611129305729513866951678348552306 76
UVM_ERROR @ 75281385 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 75281385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 26483658432396710105942979656492019251998030761300062773956620241896423689582 192
UVM_ERROR @ 289982620 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 289982620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---