kmac Simulation Results

Simulation Results: kmac

12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.50 %

code
92.50 %

assert
97.74 %

func
96.26 %

line
97.69 %

branch
96.04 %

cond
94.41 %

toggle
100.00 %

FSM
74.38 %

Validation stages

V1		100.00%
V2		98.93%
V2S		100.00%
V3		90.00%

140/140 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	kmac_smoke	60.410s	3775.139us	50	50	100.00
csr_hw_reset				5	5	100.00
	kmac_csr_hw_reset	1.480s	34.099us	5	5	100.00
csr_rw				20	20	100.00
	kmac_csr_rw	1.420s	97.521us	20	20	100.00
csr_bit_bash				5	5	100.00
	kmac_csr_bit_bash	14.180s	547.515us	5	5	100.00
csr_aliasing				5	5	100.00
	kmac_csr_aliasing	8.740s	2000.630us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	kmac_csr_mem_rw_with_rand_reset	3.170s	612.878us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	kmac_csr_rw	1.420s	97.521us	20	20	100.00
	kmac_csr_aliasing	8.740s	2000.630us	5	5	100.00
mem_walk				5	5	100.00
	kmac_mem_walk	1.060s	11.286us	5	5	100.00
mem_partial_access				5	5	100.00
	kmac_mem_partial_access	1.730s	21.664us	5	5	100.00

831/840 passed

98.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
long_msg_and_output				50	50	100.00
	kmac_long_msg_and_output	3485.820s	616181.576us	50	50	100.00
burst_write				50	50	100.00
	kmac_burst_write	920.550s	71767.295us	50	50	100.00
test_vectors				40	40	100.00
	kmac_test_vectors_sha3_224	1909.190s	409671.995us	5	5	100.00
	kmac_test_vectors_sha3_256	1985.650s	358321.059us	5	5	100.00
	kmac_test_vectors_sha3_384	1336.330s	306394.078us	5	5	100.00
	kmac_test_vectors_sha3_512	876.600s	94971.538us	5	5	100.00
	kmac_test_vectors_shake_128	2093.250s	110596.164us	5	5	100.00
	kmac_test_vectors_shake_256	1500.560s	59305.573us	5	5	100.00
	kmac_test_vectors_kmac	2.500s	122.980us	5	5	100.00
	kmac_test_vectors_kmac_xof	2.920s	319.448us	5	5	100.00
sideload				50	50	100.00
	kmac_sideload	404.570s	45266.911us	50	50	100.00
app				50	50	100.00
	kmac_app	280.020s	63859.754us	50	50	100.00
app_with_partial_data				10	10	100.00
	kmac_app_with_partial_data	249.770s	17644.647us	10	10	100.00
entropy_refresh				50	50	100.00
	kmac_entropy_refresh	325.370s	16959.552us	50	50	100.00
error				50	50	100.00
	kmac_error	381.590s	12709.711us	50	50	100.00
key_error				50	50	100.00
	kmac_key_error	19.070s	11145.680us	50	50	100.00
sideload_invalid				41	50	82.00
	kmac_sideload_invalid	149.420s	10034.773us	41	50	82.00
edn_timeout_error				20	20	100.00
	kmac_edn_timeout_error	38.650s	6166.921us	20	20	100.00
entropy_mode_error				20	20	100.00
	kmac_entropy_mode_error	40.330s	29516.883us	20	20	100.00
entropy_ready_error				10	10	100.00
	kmac_entropy_ready_error	72.790s	32039.574us	10	10	100.00
lc_escalation				50	50	100.00
	kmac_lc_escalation	30.290s	2524.942us	50	50	100.00
stress_all				50	50	100.00
	kmac_stress_all	1670.790s	143997.616us	50	50	100.00
intr_test				50	50	100.00
	kmac_intr_test	1.180s	221.402us	50	50	100.00
alert_test				50	50	100.00
	kmac_alert_test	1.210s	78.888us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	kmac_tl_errors	4.350s	159.853us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	kmac_tl_errors	4.350s	159.853us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	kmac_csr_hw_reset	1.480s	34.099us	5	5	100.00
	kmac_csr_rw	1.420s	97.521us	20	20	100.00
	kmac_csr_aliasing	8.740s	2000.630us	5	5	100.00
	kmac_same_csr_outstanding	3.240s	750.384us	20	20	100.00
tl_d_partial_access				50	50	100.00
	kmac_csr_hw_reset	1.480s	34.099us	5	5	100.00
	kmac_csr_rw	1.420s	97.521us	20	20	100.00
	kmac_csr_aliasing	8.740s	2000.630us	5	5	100.00
	kmac_same_csr_outstanding	3.240s	750.384us	20	20	100.00

V2S

495/495 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	kmac_shadow_reg_errors	2.570s	506.851us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	kmac_shadow_reg_errors	2.570s	506.851us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	kmac_shadow_reg_errors	2.570s	506.851us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	kmac_shadow_reg_errors	2.570s	506.851us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	kmac_shadow_reg_errors_with_csr_rw	5.520s	206.525us	20	20	100.00
tl_intg_err				25	25	100.00
	kmac_sec_cm	88.040s	40313.319us	5	5	100.00
	kmac_tl_intg_err	5.780s	1615.762us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	kmac_tl_intg_err	5.780s	1615.762us	20	20	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	kmac_lc_escalation	30.290s	2524.942us	50	50	100.00
sec_cm_sw_key_key_masking				50	50	100.00
	kmac_smoke	60.410s	3775.139us	50	50	100.00
sec_cm_key_sideload				50	50	100.00
	kmac_sideload	404.570s	45266.911us	50	50	100.00
sec_cm_cfg_shadowed_config_shadow				20	20	100.00
	kmac_shadow_reg_errors	2.570s	506.851us	20	20	100.00
sec_cm_fsm_sparse				5	5	100.00
	kmac_sec_cm	88.040s	40313.319us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	kmac_sec_cm	88.040s	40313.319us	5	5	100.00
sec_cm_packer_ctr_redun				5	5	100.00
	kmac_sec_cm	88.040s	40313.319us	5	5	100.00
sec_cm_cfg_shadowed_config_regwen				50	50	100.00
	kmac_smoke	60.410s	3775.139us	50	50	100.00
sec_cm_fsm_global_esc				50	50	100.00
	kmac_lc_escalation	30.290s	2524.942us	50	50	100.00
sec_cm_fsm_local_esc				5	5	100.00
	kmac_sec_cm	88.040s	40313.319us	5	5	100.00
sec_cm_absorbed_ctrl_mubi				10	10	100.00
	kmac_mubi	258.160s	16041.512us	10	10	100.00
sec_cm_sw_cmd_ctrl_sparse				50	50	100.00
	kmac_smoke	60.410s	3775.139us	50	50	100.00

9/10 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				9	10	90.00
	kmac_stress_all_with_rand_reset	132.740s	30874.562us	9	10	90.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)
	kmac_sideload_invalid	23901720984131703904101573065913346368074511652907311786952880693044626466021	76	UVM_FATAL @ 10063220255 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x86b31000, Comparison=CompareOpEq, exp_data=0x1, call_count=3) UVM_INFO @ 10063220255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	40542469181352848126247618012791478650847697530137552784909433668485602452009	76	UVM_FATAL @ 10040829308 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3f038000, Comparison=CompareOpEq, exp_data=0x1, call_count=3) UVM_INFO @ 10040829308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	15288102613791521979664108390482515475331399823742469057050202221022616822930	76	UVM_FATAL @ 10096035519 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc8a28000, Comparison=CompareOpEq, exp_data=0x1, call_count=3) UVM_INFO @ 10096035519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	31825140452596841923285732969033847561584773877618162135882178948572137306544	76	UVM_FATAL @ 10095083058 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdee95000, Comparison=CompareOpEq, exp_data=0x1, call_count=3) UVM_INFO @ 10095083058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [] vs [*])
	kmac_stress_all_with_rand_reset	14320167587246446228121747542293210524961944200914832389558049844609667652299	233	UVM_ERROR @ 14383648977 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0]) UVM_INFO @ 14383648977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=10)
	kmac_sideload_invalid	23517819962927370292837115537224847865053520866074787328666758319224056824184	83	UVM_FATAL @ 10343982957 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd3f8d000, Comparison=CompareOpEq, exp_data=0x1, call_count=10) UVM_INFO @ 10343982957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=8)
	kmac_sideload_invalid	27812366115505038322948192811399080453678955249677791155943209707646937831575	82	UVM_FATAL @ 10055770194 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaa566000, Comparison=CompareOpEq, exp_data=0x1, call_count=8) UVM_INFO @ 10055770194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=6)
	kmac_sideload_invalid	112785166926269206891895808748169261251706317692215383231463341091530628787666	80	UVM_FATAL @ 10034772629 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6246d000, Comparison=CompareOpEq, exp_data=0x1, call_count=6) UVM_INFO @ 10034772629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=12)
	kmac_sideload_invalid	10177467432693510637024519232566415745068179980069352319128485399853154413504	87	UVM_FATAL @ 10065568204 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2a143000, Comparison=CompareOpEq, exp_data=0x1, call_count=12) UVM_INFO @ 10065568204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=2)
	kmac_sideload_invalid	46343220588942995954526559008263603129967326632892165440098781477975408113924	75	UVM_FATAL @ 10011064341 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1db5e000, Comparison=CompareOpEq, exp_data=0x1, call_count=2) UVM_INFO @ 10011064341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---