Simulation Results: mbx

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.63 %
  • code
  • 91.55 %
  • assert
  • 97.01 %
  • func
  • 86.33 %
  • block
  • 96.68 %
  • line
  • 96.64 %
  • branch
  • 91.89 %
  • toggle
  • 86.12 %
Validation stages
V1
100.00%
V2
98.80%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 2 2 100.00
mbx_smoke 91.000s 4767.232us 2 2 100.00
csr_hw_reset 5 5 100.00
mbx_csr_hw_reset 2.000s 73.109us 5 5 100.00
csr_rw 20 20 100.00
mbx_csr_rw 2.000s 25.281us 20 20 100.00
csr_bit_bash 5 5 100.00
mbx_csr_bit_bash 5.000s 583.633us 5 5 100.00
csr_aliasing 5 5 100.00
mbx_csr_aliasing 2.000s 46.098us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
mbx_csr_mem_rw_with_rand_reset 3.000s 33.437us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
mbx_csr_rw 2.000s 25.281us 20 20 100.00
mbx_csr_aliasing 2.000s 46.098us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 2 50.00
mbx_stress 125.000s 7810.752us 1 2 50.00
mbx_max_activity 0 2 0.00
mbx_stress_zero_delays 33.000s 120.063us 0 2 0.00
mbx_imbx_oob 2 2 100.00
mbx_imbx_oob 63.000s 3638.690us 2 2 100.00
mbx_doe_intr_msg 5 5 100.00
mbx_doe_intr_msg 53.000s 5958.175us 5 5 100.00
alert_test 50 50 100.00
mbx_alert_test 26.000s 40.650us 50 50 100.00
intr_test 50 50 100.00
mbx_intr_test 2.000s 42.787us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
mbx_tl_errors 6.000s 662.405us 20 20 100.00
tl_d_illegal_access 20 20 100.00
mbx_tl_errors 6.000s 662.405us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
mbx_csr_hw_reset 2.000s 73.109us 5 5 100.00
mbx_csr_rw 2.000s 25.281us 20 20 100.00
mbx_csr_aliasing 2.000s 46.098us 5 5 100.00
mbx_same_csr_outstanding 3.000s 101.236us 20 20 100.00
tl_d_partial_access 50 50 100.00
mbx_csr_hw_reset 2.000s 73.109us 5 5 100.00
mbx_csr_rw 2.000s 25.281us 20 20 100.00
mbx_csr_aliasing 2.000s 46.098us 5 5 100.00
mbx_same_csr_outstanding 3.000s 101.236us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
mbx_sec_cm 27.000s 17.355us 5 5 100.00
mbx_tl_intg_err 3.000s 262.964us 20 20 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed
mbx_stress 62657068146746066242104709297833116336811481462146060395744558776040340581196 194
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 1280489620 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
UVM_ERROR @ 1280489620 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 1280489620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress_zero_delays 7872676285253039303321345448307748546056277612783318597214543773060435597315 434
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 120063054 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
UVM_ERROR @ 120063054 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 120063054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress_zero_delays 92351495156191037769786575354535573729119602989086850803758246289968086539086 687
UVM_ERROR @ 139095784 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 139095784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---