Simulation Results: otbn

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.93 %
  • code
  • 97.08 %
  • assert
  • 96.72 %
  • func
  • 100.00 %
  • block
  • 99.60 %
  • line
  • 99.70 %
  • branch
  • 95.42 %
  • toggle
  • 93.20 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.42%
V2S
97.57%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 12.000s 72.059us 1 1 100.00
single_binary 100 100 100.00
otbn_single 77.000s 326.911us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 8.000s 34.410us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 8.000s 26.026us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 15.000s 107.978us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 7.000s 38.004us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 13.000s 38.313us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 8.000s 26.026us 20 20 100.00
otbn_csr_aliasing 7.000s 38.004us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 46.000s 4384.907us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 24.000s 6987.535us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 9 10 90.00
otbn_reset 52.000s 277.657us 9 10 90.00
multi_error 1 1 100.00
otbn_multi_err 57.000s 281.609us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 75.000s 250.993us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 98.000s 3825.318us 10 10 100.00
lc_escalation 59 60 98.33
otbn_escalate 378.000s 1281.576us 59 60 98.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 7.000s 30.327us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 20.000s 87.907us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 6.000s 20.368us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 9.000s 47.660us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 13.000s 121.264us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 13.000s 121.264us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 8.000s 34.410us 5 5 100.00
otbn_csr_rw 8.000s 26.026us 20 20 100.00
otbn_csr_aliasing 7.000s 38.004us 5 5 100.00
otbn_same_csr_outstanding 8.000s 24.165us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 8.000s 34.410us 5 5 100.00
otbn_csr_rw 8.000s 26.026us 20 20 100.00
otbn_csr_aliasing 7.000s 38.004us 5 5 100.00
otbn_same_csr_outstanding 8.000s 24.165us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 10.000s 27.958us 10 10 100.00
otbn_dmem_err 13.000s 49.778us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 10.000s 114.535us 5 5 100.00
otbn_controller_ispr_rdata_err 11.000s 116.641us 5 5 100.00
otbn_mac_bignum_acc_err 72.000s 255.916us 5 5 100.00
otbn_urnd_err 5.000s 28.847us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 13.000s 48.762us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 7.000s 21.483us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 10.000s 50.591us 10 10 100.00
tl_intg_err 23 25 92.00
otbn_tl_intg_err 43.000s 335.137us 20 20 100.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
passthru_mem_tl_intg_err 19 20 95.00
otbn_passthru_mem_tl_intg_err 61.000s 298.861us 19 20 95.00
prim_fsm_check 3 5 60.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
prim_count_check 3 5 60.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 12.000s 72.059us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 13.000s 49.778us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 10.000s 27.958us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 43.000s 335.137us 20 20 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 378.000s 1281.576us 59 60 98.33
sec_cm_controller_fsm_local_esc 38 40 95.00
otbn_imem_err 10.000s 27.958us 10 10 100.00
otbn_dmem_err 13.000s 49.778us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 30.327us 5 5 100.00
otbn_illegal_mem_acc 13.000s 48.762us 5 5 100.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
sec_cm_controller_fsm_sparse 3 5 60.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 77.000s 326.911us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 38 40 95.00
otbn_imem_err 10.000s 27.958us 10 10 100.00
otbn_dmem_err 13.000s 49.778us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 30.327us 5 5 100.00
otbn_illegal_mem_acc 13.000s 48.762us 5 5 100.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
sec_cm_scramble_ctrl_fsm_sparse 3 5 60.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 378.000s 1281.576us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 38 40 95.00
otbn_imem_err 10.000s 27.958us 10 10 100.00
otbn_dmem_err 13.000s 49.778us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 30.327us 5 5 100.00
otbn_illegal_mem_acc 13.000s 48.762us 5 5 100.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
sec_cm_start_stop_ctrl_fsm_sparse 3 5 60.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 77.000s 326.911us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 10.000s 23.178us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 16.000s 65.590us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 26.000s 309.532us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 26.000s 309.532us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 9.000s 21.052us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 3 5 60.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
sec_cm_stack_wr_ptr_ctr_redun 3 5 60.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 23.000s 91.078us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 3 5 60.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
sec_cm_loop_stack_ctr_redun 3 5 60.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 10.000s 17.899us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 10.000s 17.899us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 6 7 85.71
otbn_sec_wipe_err 17.000s 118.767us 6 7 85.71
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 77.000s 326.911us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 77.000s 326.911us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 77.000s 326.911us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 75.000s 250.993us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 77.000s 326.911us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 77.000s 326.911us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 14.000s 124.738us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 77.000s 326.911us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 3 5 60.00
otbn_sec_cm 249.000s 2520.572us 3 5 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
otbn_stress_all_with_rand_reset 473.000s 11769.117us 5 10 50.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 14801726892402819772142587477262567864245127868203204099202343212314244684035 83
UVM_FATAL @ 13219438 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 13219438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 67931292281541851833236771912504743709895882396063660207307739318366753358879 372
UVM_FATAL @ 2859526063 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 2859526063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed
otbn_sec_cm 12365593323975256813309236427863656513438463239848302460092919340362156539213 89
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 4682565 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 4682565 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 4682565 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 4682565 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 4682565 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
otbn_sec_cm 114705156519986665090742970157110215393261370713273841757661827443730584402421 108
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 69829683 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 69829683 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 69829683 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 69829683 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 69829683 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_sec_wipe_err 9598574085564138527632368774505319032236352220521700106585201920935311060466 112
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 118767419 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 118767419 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 118767419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 106559741212039639339489654976403191680454737279344401001936164354185641461713 121
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 98454778 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 98454778 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 98454778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 46214342156303233194001725345145205404761260084214368689100515890099181733255 156
UVM_ERROR @ 123944445 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123944445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 44454395331071173355045171446175161103603444799526050310605427508478824766563 250
UVM_ERROR @ 3453956317 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3453956317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 55909629612725434266012034994984029208839016296250572376691670696354865357826 476
UVM_ERROR @ 11769117304 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11769117304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 97232948070369931688322282720175106997198834598961745182148380054688655138684 170
UVM_FATAL @ 2372155766 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 2372155766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
otbn_reset 41273016905957024010507862548839777847236585021910276041695842879763444199597 151
UVM_FATAL @ 277657079 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 277657079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---