Simulation Results: rom_ctrl

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.54 %
  • code
  • 99.55 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
88.05%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.630s 331.893us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 9.200s 133.995us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 8.070s 687.082us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 9.120s 1051.336us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 6.750s 169.601us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.750s 145.255us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 8.070s 687.082us 20 20 100.00
rom_ctrl_csr_aliasing 6.750s 169.601us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 6.170s 171.289us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 6.060s 288.302us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 4.690s 314.149us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 21.960s 2150.591us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 7.710s 546.502us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 8.260s 542.516us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 11.190s 549.008us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 11.190s 549.008us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.200s 133.995us 5 5 100.00
rom_ctrl_csr_rw 8.070s 687.082us 20 20 100.00
rom_ctrl_csr_aliasing 6.750s 169.601us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.390s 171.242us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.200s 133.995us 5 5 100.00
rom_ctrl_csr_rw 8.070s 687.082us 20 20 100.00
rom_ctrl_csr_aliasing 6.750s 169.601us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.390s 171.242us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.600s 3872.438us 18 20 90.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 38.540s 12015.605us 20 20 100.00
tl_intg_err 22 25 88.00
rom_ctrl_sec_cm 274.610s 1231.406us 2 5 40.00
rom_ctrl_tl_intg_err 69.460s 322.339us 20 20 100.00
prim_fsm_check 2 5 40.00
rom_ctrl_sec_cm 274.610s 1231.406us 2 5 40.00
prim_count_check 2 5 40.00
rom_ctrl_sec_cm 274.610s 1231.406us 2 5 40.00
sec_cm_checker_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.600s 3872.438us 18 20 90.00
sec_cm_checker_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.600s 3872.438us 18 20 90.00
sec_cm_checker_fsm_local_esc 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.600s 3872.438us 18 20 90.00
sec_cm_compare_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.600s 3872.438us 18 20 90.00
sec_cm_compare_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.600s 3872.438us 18 20 90.00
sec_cm_compare_ctr_redun 2 5 40.00
rom_ctrl_sec_cm 274.610s 1231.406us 2 5 40.00
sec_cm_fsm_sparse 2 5 40.00
rom_ctrl_sec_cm 274.610s 1231.406us 2 5 40.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.630s 331.893us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.630s 331.893us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.630s 331.893us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 69.460s 322.339us 20 20 100.00
sec_cm_bus_local_esc 20 22 90.91
rom_ctrl_corrupt_sig_fatal_chk 123.600s 3872.438us 18 20 90.00
rom_ctrl_kmac_err_chk 7.710s 546.502us 2 2 100.00
sec_cm_mux_mubi 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.600s 3872.438us 18 20 90.00
sec_cm_mux_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.600s 3872.438us 18 20 90.00
sec_cm_ctrl_redun 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.600s 3872.438us 18 20 90.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 38.540s 12015.605us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 2 5 40.00
rom_ctrl_sec_cm 274.610s 1231.406us 2 5 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 431.840s 4617.963us 20 20 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 112190628694245682537547221853594122730729439757026096259300381268379572391280 281
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 13931912ps failed at 13931912ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 15737521ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 15737521ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
rom_ctrl_sec_cm 39902194725674863494034091978050090711713639189965829559349230520242760618898 106
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 2930094ps failed at 2930094ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 2930094ps failed at 2930094ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 42018881425073272376434195156647558431460255778699872727934022336104123733612 89
UVM_ERROR @ 864672359 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 864672359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 6381801374381503525568401595560892361475346285172589032326282087029657011709 81
UVM_ERROR @ 212198883 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 212198883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
rom_ctrl_sec_cm 77736018729766696289864045876569187305943262910721972343478710485481660168005 108
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 10359658ps failed at 10359658ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 10398120ps failed at 10398120ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'