Simulation Results: rom_ctrl

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.68 %
  • code
  • 98.74 %
  • assert
  • 95.49 %
  • func
  • 98.81 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 95.39 %
  • toggle
  • 99.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.57%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 11.830s 219.714us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 12.710s 215.924us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 8.500s 304.020us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 9.150s 300.785us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 9.630s 3716.038us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.540s 4167.117us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 8.500s 304.020us 20 20 100.00
rom_ctrl_csr_aliasing 9.630s 3716.038us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 8.540s 698.598us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 8.710s 1161.520us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 11.170s 1111.434us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 53.870s 1069.125us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 16.700s 397.353us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 15.350s 3984.422us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 13.250s 1068.985us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 13.250s 1068.985us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 12.710s 215.924us 5 5 100.00
rom_ctrl_csr_rw 8.500s 304.020us 20 20 100.00
rom_ctrl_csr_aliasing 9.630s 3716.038us 5 5 100.00
rom_ctrl_same_csr_outstanding 12.600s 1035.239us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 12.710s 215.924us 5 5 100.00
rom_ctrl_csr_rw 8.500s 304.020us 20 20 100.00
rom_ctrl_csr_aliasing 9.630s 3716.038us 5 5 100.00
rom_ctrl_same_csr_outstanding 12.600s 1035.239us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 255.020s 7228.087us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 45.850s 1588.690us 20 20 100.00
tl_intg_err 20 25 80.00
rom_ctrl_tl_intg_err 126.930s 611.978us 20 20 100.00
rom_ctrl_sec_cm 662.430s 8522.207us 0 5 0.00
prim_fsm_check 0 5 0.00
rom_ctrl_sec_cm 662.430s 8522.207us 0 5 0.00
prim_count_check 0 5 0.00
rom_ctrl_sec_cm 662.430s 8522.207us 0 5 0.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 255.020s 7228.087us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 255.020s 7228.087us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 255.020s 7228.087us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 255.020s 7228.087us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 255.020s 7228.087us 20 20 100.00
sec_cm_compare_ctr_redun 0 5 0.00
rom_ctrl_sec_cm 662.430s 8522.207us 0 5 0.00
sec_cm_fsm_sparse 0 5 0.00
rom_ctrl_sec_cm 662.430s 8522.207us 0 5 0.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 11.830s 219.714us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 11.830s 219.714us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 11.830s 219.714us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 126.930s 611.978us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 255.020s 7228.087us 20 20 100.00
rom_ctrl_kmac_err_chk 16.700s 397.353us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 255.020s 7228.087us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 255.020s 7228.087us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 255.020s 7228.087us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 45.850s 1588.690us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
rom_ctrl_sec_cm 662.430s 8522.207us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 341.480s 4217.799us 20 20 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 79847075005776339125841234739801601197902774670965254292578210348232460076361 230
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 89122386ps failed at 89122386ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 99809892ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 99809892ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 16080436711472165413257172194399728972146892694366107227799561265215723688902 234
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 27057841ps failed at 27057841ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 27057841ps failed at 27057841ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 20548997252847760410604830057103497188504114989106155229365647025642928027236 280
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 32087320ps failed at 32087320ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 32087320ps failed at 32087320ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
rom_ctrl_sec_cm 41038708596011877190653118071159750531964969904980888764317950623833159837641 118
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 10910959ps failed at 10910959ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 15762512ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 15762512ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
rom_ctrl_sec_cm 100193656473976841377334956420607395299880639360535800358602053922841227681278 181
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 125106643ps failed at 125106643ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 154356703ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 154356703ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))