Simulation Results: rstmgr

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.56 %
  • code
  • 99.59 %
  • assert
  • 97.62 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.20%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.360s 66.877us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.290s 92.564us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.030s 37.190us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 4.220s 197.186us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.470s 40.399us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.410s 95.218us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.030s 37.190us 20 20 100.00
rstmgr_csr_aliasing 1.470s 40.399us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.880s 187.010us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 1.230s 46.349us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.320s 82.144us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 5.840s 806.384us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 5.840s 806.384us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 5.840s 806.384us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 5.840s 806.384us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 43.200s 6403.722us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 3.440s 367.933us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 2.430s 86.849us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 2.430s 86.849us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.290s 92.564us 5 5 100.00
rstmgr_csr_rw 1.030s 37.190us 20 20 100.00
rstmgr_csr_aliasing 1.470s 40.399us 5 5 100.00
rstmgr_same_csr_outstanding 1.180s 74.391us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.290s 92.564us 5 5 100.00
rstmgr_csr_rw 1.030s 37.190us 20 20 100.00
rstmgr_csr_aliasing 1.470s 40.399us 5 5 100.00
rstmgr_same_csr_outstanding 1.180s 74.391us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 31.840s 6762.266us 5 5 100.00
rstmgr_tl_intg_err 5.400s 889.489us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 31.840s 6762.266us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 31.840s 6762.266us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 5.400s 889.489us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.380s 56.194us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 48 50 96.00
rstmgr_leaf_rst_cnsty 3.960s 463.555us 48 50 96.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 2.320s 291.494us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 31.840s 6762.266us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.030s 37.190us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.030s 37.190us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:*
rstmgr_leaf_rst_cnsty 94358253069822809798212898486719806114926061520319189382894346813403649183737 76
UVM_ERROR @ 38520229 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
UVM_INFO @ 38520229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rstmgr_leaf_rst_cnsty 110731285449316256139526573338312942652308834549302396022442581798807125520360 81
UVM_ERROR @ 59658776 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
UVM_INFO @ 59658776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---