| V1 |
|
100.00% |
| V2 |
|
93.75% |
| V2S |
|
100.00% |
| V3 |
|
37.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.440s | 166.760us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.850s | 223.325us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.800s | 39.224us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 4.140s | 419.705us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 1.060s | 116.040us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.440s | 125.228us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.800s | 39.224us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.060s | 116.040us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 0 | 20 | 0.00 | |||
| rv_timer_random_reset | 9.080s | 13975.095us | 0 | 20 | 0.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 3.420s | 2055.118us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 373.260s | 896063.552us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 373.260s | 896063.552us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 5.330s | 7973.012us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.860s | 17.150us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.800s | 62.540us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.880s | 377.842us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.880s | 377.842us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.850s | 223.325us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.800s | 39.224us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.060s | 116.040us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.990s | 64.133us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.850s | 223.325us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.800s | 39.224us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.060s | 116.040us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.990s | 64.133us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 0.970s | 64.195us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.510s | 283.720us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.510s | 283.720us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 0 | 10 | 0.00 | |||
| rv_timer_min | 1.350s | 2840.362us | 0 | 10 | 0.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.110s | 115.819us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 15 | 20 | 75.00 | |||
| rv_timer_stress_all_with_rand_reset | 73.390s | 37057.025us | 15 | 20 | 75.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_min | 60412190429466978681891529864550591937605855436211722617536620103740101049108 | 72 |
UVM_FATAL @ 65980717 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x53fb5504) == 0x1
UVM_INFO @ 65980717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 21536215252853268293190490209100965475113932441643405091388327796204696720796 | 72 |
UVM_FATAL @ 549566517 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2005a704) == 0x1
UVM_INFO @ 549566517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 85281575328519806600899804916825236721351411606166059757335978864425091612514 | 72 |
UVM_FATAL @ 113690320 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x36fbe704) == 0x1
UVM_INFO @ 113690320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 95844618644730153621500663563001997953470744012061861912544005121010323420646 | 72 |
UVM_FATAL @ 236905655 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6801e304) == 0x1
UVM_INFO @ 236905655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 67709213058698145024748955655772976141521689778505041529626337032823253879273 | 73 |
UVM_FATAL @ 2840361527 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xfbd18904) == 0x1
UVM_INFO @ 2840361527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 86701238456777009609491899833263031401702304167949537171863636033896647376478 | 72 |
UVM_FATAL @ 477597756 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x48001f04) == 0x1
UVM_INFO @ 477597756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 20536149247116391368438558111561159176233420065627296284134424469123001755188 | 72 |
UVM_FATAL @ 219143194 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x89aadf04) == 0x1
UVM_INFO @ 219143194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 82862361874814056959489801821799366513717029432657991168575977329290446779975 | 72 |
UVM_FATAL @ 160036874 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe0747f04) == 0x1
UVM_INFO @ 160036874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 107887411090244875242094950051844445714405181133108068218241769998708948375140 | 72 |
UVM_FATAL @ 232690615 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc940bd04) == 0x1
UVM_INFO @ 232690615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 76272848483071971597208489937285436333317739503921144927405587218695613099450 | 72 |
UVM_FATAL @ 1469658575 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa1702704) == 0x1
UVM_INFO @ 1469658575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 7177028461799406897736428639097584181223130093825820765525816835280496179000 | 72 |
UVM_FATAL @ 271727765 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x594b4704) == 0x1
UVM_INFO @ 271727765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 9742023401018432342306493424913274548509629447620191917600785504885099289717 | 72 |
UVM_FATAL @ 480934735 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x78a0c304) == 0x1
UVM_INFO @ 480934735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 7983568279371611557429774697124995017675936525373444358858050055242975754236 | 72 |
UVM_FATAL @ 111208709 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x39f72504) == 0x1
UVM_INFO @ 111208709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 60711337904391780375028568013501826937726151060570134563366784190670078723332 | 72 |
UVM_FATAL @ 21347169838 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc3029904) == 0x1
UVM_INFO @ 21347169838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 42840371420214752105251011917364390146120599831341308336788999802556607928166 | 73 |
UVM_FATAL @ 111130298 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf1efbb04) == 0x1
UVM_INFO @ 111130298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 45762115485731035338776825765359542716371001691814785220149875205129755690314 | 72 |
UVM_FATAL @ 130836182 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb023a704) == 0x1
UVM_INFO @ 130836182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 42880334413343369073191284095178949737106145341080660274233393432664529739256 | 72 |
UVM_FATAL @ 1321735375 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2385a104) == 0x1
UVM_INFO @ 1321735375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 81662016663207098932249947652076831903267422616457513980826118418666106278899 | 72 |
UVM_FATAL @ 299775108 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x1bed0904) == 0x1
UVM_INFO @ 299775108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 100738406090989519801092092200681564429538222290333679946498897566641569431408 | 72 |
UVM_FATAL @ 227098047 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc60e4104) == 0x1
UVM_INFO @ 227098047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 81297440178374960239121490620210088682728155431416283348746263270277691190679 | 72 |
UVM_FATAL @ 13975094599 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xda4c6704) == 0x1
UVM_INFO @ 13975094599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 104692873362384453361898152068729476441477452823739503639323424746016812161020 | 72 |
UVM_FATAL @ 81926333 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xcdf30704) == 0x1
UVM_INFO @ 81926333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 67255556490326685892374595216214926392449359111801899069185877493260383431874 | 73 |
UVM_FATAL @ 164770505 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x834edf04) == 0x1
UVM_INFO @ 164770505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 22863682981420333792144491670521828521428654834087663253493399732618641810864 | 73 |
UVM_FATAL @ 558946376 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x21d6fb04) == 0x1
UVM_INFO @ 558946376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 15439300857832994135873532003117055322889627705136658697856674561766938357810 | 72 |
UVM_FATAL @ 106727557 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x22ea2104) == 0x1
UVM_INFO @ 106727557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 3187055295028492792962332569219065274832379160116631755653279333203732099857 | 72 |
UVM_FATAL @ 120790513 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x1416ed04) == 0x1
UVM_INFO @ 120790513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 58782188969317667568545680678040090044035242255632867440305321620022492010934 | 72 |
UVM_FATAL @ 191274671 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd4155104) == 0x1
UVM_INFO @ 191274671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 28847167224352869128381694398873736792764029069572948112815471820708794090045 | 72 |
UVM_FATAL @ 88740605 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3b646f04) == 0x1
UVM_INFO @ 88740605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 93625983476833749574838985446762767957188403952218126348709356557289194606250 | 72 |
UVM_FATAL @ 497285388 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x14968f04) == 0x1
UVM_INFO @ 497285388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 34140474562057755075669474436150950821114255581384640863489141585680844649138 | 72 |
UVM_FATAL @ 434143740 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x71445904) == 0x1
UVM_INFO @ 434143740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 115671248240104140157562116895050457491270099486702464284106708690205268544401 | 72 |
UVM_FATAL @ 191379286 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7f0dbf04) == 0x1
UVM_INFO @ 191379286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 62366038573683649829486473026915283439679171220948182422689273534287886394751 | 72 |
UVM_ERROR @ 93985519 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 93985519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 104108632304482234349090240323128789255846790953206396517677249217927774304863 | 72 |
UVM_ERROR @ 44033702 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 44033702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 88609529340799408913409058811381774365241295396410435631885044406877581527277 | 73 |
UVM_ERROR @ 172036467 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 172036467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 44507106329802177480675944182263084051535971273019410523219648142074381609734 | 72 |
UVM_ERROR @ 49335156 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 49335156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 79329796460293627198156461902526150103664913690722223835964221903250859405527 | 72 |
UVM_ERROR @ 42559614 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 42559614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 45967649987832237535564165648637286068661917165836746260763917829854659593471 | 73 |
UVM_ERROR @ 170353206 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 170353206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 60333011375039602607442426528057534026612424153328725743170041514707281291029 | 72 |
UVM_ERROR @ 43329170 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 43329170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 114567270390075023669593125356150115701945956079582311183925397408092247816256 | 73 |
UVM_ERROR @ 115818909 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 115818909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 75772492408268879506190767214290669811423640879632001711380599449195665770215 | 72 |
UVM_ERROR @ 48253074 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 48253074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| rv_timer_max | 53921158981684711781416127693422757740844532472920381684051666484595053473581 | 72 |
UVM_ERROR @ 300728241 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 300728241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 46119566859535312737973680347748827757760591139114351198891878713440323027926 | 285 |
UVM_FATAL @ 46433081529 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 46433081529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| rv_timer_stress_all_with_rand_reset | 86884508349194739377270509071588440698323665416946483918833114544705253486365 | 135 |
UVM_FATAL @ 42800530 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 42800530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| rv_timer_stress_all_with_rand_reset | 99765018330945955619865315836992545473934842153497110807936369479964193250919 | 241 |
UVM_FATAL @ 2641250036 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 2641250036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 81102222174622799572494411877358354203822589348268736657367831266453973956415 | 125 |
UVM_ERROR @ 99112387 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 99112387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| rv_timer_stress_all_with_rand_reset | 27694568623444210529299834307845500613580596801416065270780654157678753749692 | 168 |
UVM_ERROR @ 243921786 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 243921786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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