Simulation Results: spi_host

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.55 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 90.42 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.82%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 93.000s 2710.490us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 27.000s 30.069us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 27.000s 47.553us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 27.000s 806.646us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 27.000s 18.084us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 27.000s 56.135us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 27.000s 47.553us 20 20 100.00
spi_host_csr_aliasing 27.000s 18.084us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 27.000s 18.108us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 27.000s 22.650us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 4.000s 110.175us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 20.000s 576.585us 50 50 100.00
spi_host_error_cmd 3.000s 20.767us 50 50 100.00
spi_host_event 206.000s 22983.990us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 10.000s 480.119us 50 50 100.00
speed 50 50 100.00
spi_host_speed 10.000s 480.119us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 10.000s 480.119us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 116.000s 4749.704us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 3.000s 115.584us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 10.000s 480.119us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 10.000s 480.119us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 93.000s 2710.490us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 93.000s 2710.490us 50 50 100.00
stress_all 48 50 96.00
spi_host_stress_all 1916.000s 1000000.000us 48 50 96.00
spien 50 50 100.00
spi_host_spien 169.000s 9779.386us 50 50 100.00
stall 50 50 100.00
spi_host_status_stall 727.000s 42302.811us 50 50 100.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 22.000s 9611.629us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 20.000s 576.585us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 3.000s 19.295us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 27.000s 14.686us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 29.000s 168.546us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 29.000s 168.546us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 27.000s 30.069us 5 5 100.00
spi_host_csr_rw 27.000s 47.553us 20 20 100.00
spi_host_csr_aliasing 27.000s 18.084us 5 5 100.00
spi_host_same_csr_outstanding 27.000s 23.655us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 27.000s 30.069us 5 5 100.00
spi_host_csr_rw 27.000s 47.553us 20 20 100.00
spi_host_csr_aliasing 27.000s 18.084us 5 5 100.00
spi_host_same_csr_outstanding 27.000s 23.655us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_tl_intg_err 28.000s 94.623us 20 20 100.00
spi_host_sec_cm 3.000s 120.340us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 28.000s 94.623us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_host_upper_range_clkdiv 738.000s 90369.856us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_stress_all 62417254368215850650689239305608698010152620657942836356871419241655244578421 225
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_stress_all 38826679588335325989700635049623284707484020590757090536278945032326215038751 126
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---