Simulation Results: sram_ctrl

 
12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.49%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 91.390s 807.224us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.060s 30.188us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.080s 37.680us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.610s 122.475us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.120s 21.411us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.720s 2936.335us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.080s 37.680us 20 20 100.00
sram_ctrl_csr_aliasing 1.120s 21.411us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 366.530s 74743.135us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 179.690s 5176.065us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1319.360s 118477.127us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 390.150s 5032.789us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2645.510s 751991.917us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1140.170s 20154.952us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 147.820s 37277.904us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1267.550s 8866.127us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 105.030s 1062.947us 50 50 100.00
sram_ctrl_partial_access_b2b 644.340s 88772.182us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 104.780s 3178.231us 50 50 100.00
sram_ctrl_throughput_w_partial_write 103.490s 3166.538us 50 50 100.00
sram_ctrl_throughput_w_readback 98.520s 1910.202us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1270.360s 20148.877us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 5.200s 3040.316us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 8710.360s 4726857.311us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.050s 40.377us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.440s 155.975us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.440s 155.975us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.060s 30.188us 5 5 100.00
sram_ctrl_csr_rw 1.080s 37.680us 20 20 100.00
sram_ctrl_csr_aliasing 1.120s 21.411us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.220s 393.447us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.060s 30.188us 5 5 100.00
sram_ctrl_csr_rw 1.080s 37.680us 20 20 100.00
sram_ctrl_csr_aliasing 1.120s 21.411us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.220s 393.447us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 54.550s 7693.048us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.100s 39.160us 0 5 0.00
sram_ctrl_tl_intg_err 4.190s 674.687us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.100s 39.160us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.190s 674.687us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1270.360s 20148.877us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1270.360s 20148.877us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.080s 37.680us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1267.550s 8866.127us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1267.550s 8866.127us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1267.550s 8866.127us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 147.820s 37277.904us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 45 50 90.00
sram_ctrl_mubi_enc_err 9.050s 1962.895us 45 50 90.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 54.550s 7693.048us 20 20 100.00
sec_cm_mem_readback 42 50 84.00
sram_ctrl_readback_err 12.180s 13165.790us 42 50 84.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 91.390s 807.224us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 91.390s 807.224us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1267.550s 8866.127us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.100s 39.160us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 147.820s 37277.904us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.100s 39.160us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.100s 39.160us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 91.390s 807.224us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.100s 39.160us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 115.270s 1833.675us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 44704931443526894698496084588268589956650220747283555983684235369931133864793 97
UVM_ERROR @ 2182925 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2182925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 41256758795235526070861343365081404044841689104187360108730781653984630716223 97
UVM_ERROR @ 10323806 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 10323806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 1205035506777377460968577915753990655785870123118437879465741604778852346528 97
UVM_ERROR @ 1638423 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1638423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 18961874352398939007297881509432229679014049899661082660957447039588757254036 99
UVM_ERROR @ 39160150 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 39160150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 64874453520447598812726226455684931351591498899911638820618780430940386500436 97
UVM_ERROR @ 3088745 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3088745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 44234525079644474128356968461416950378968754269704496129976836206993579398621 95
UVM_ERROR @ 670636916 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x12) != exp (0x1b)
UVM_INFO @ 670636916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 84020088733670192503355697787919136520064597985949446553803550877754574757517 95
UVM_ERROR @ 2986508139 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x67) != exp (0x66)
UVM_INFO @ 2986508139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 65551907924370668569712087054932848438705259889232909360549610386247276595825 95
UVM_ERROR @ 2861752973 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5a) != exp (0x9)
UVM_INFO @ 2861752973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 66441953959565468605313487008668561452065524394640978884354267674292760026926 95
UVM_ERROR @ 4114258108 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x79) != exp (0x5d)
UVM_INFO @ 4114258108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 92194320266075192221521537604283152846338011970610605798020224029252991124076 95
UVM_ERROR @ 666852358 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7) != exp (0xf)
UVM_INFO @ 666852358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 72003686549590901638304253422613254340890915731542877630870332496832989876298 95
UVM_ERROR @ 2346648050 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6f) != exp (0x79)
UVM_INFO @ 2346648050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 23860903585794283756501059036601202630518677440774909211793631213812433495206 95
UVM_ERROR @ 3650547208 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2f) != exp (0x1e)
UVM_INFO @ 3650547208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 22066695620282575079813164518263859972651898451752352166874743279214658888634 95
UVM_ERROR @ 4434464448 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7e) != exp (0x51)
UVM_INFO @ 4434464448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 9986447935562106587315379993498849349800639233218087598561052350920313469824 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 759482446 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 759482446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 66445099235078947488866773427704119071647778383977777679455193441544162035243 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2431609200 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2431609200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 77563480091273349048483489225768911214238614627934142875271995916356084306755 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2660869514 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2660869514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 26404162237115420729695074564267686980292809623439481433364445462995856293523 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 3292695224 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 3292695224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 95729113186035410848629373348561842836581618423352464679697687048921450549490 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2150412244 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2150412244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---