sram_ctrl Simulation Results

Simulation Results: sram_ctrl

12/12/2025 17:09:52 sha: 801ac60 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.75 %

code
96.12 %

assert
95.79 %

func
98.33 %

line
99.07 %

branch
97.98 %

cond
92.90 %

toggle
90.66 %

FSM
100.00 %

Validation stages

V1		99.57%
V2		100.00%
V2S		94.10%
V3		100.00%

229/230 passed

99.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sram_ctrl_smoke	100.280s	659.833us	50	50	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	1.050s	52.141us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	1.040s	26.374us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	1.980s	171.419us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	1.120s	24.876us	5	5	100.00
csr_mem_rw_with_rand_reset				19	20	95.00
	sram_ctrl_csr_mem_rw_with_rand_reset	3.180s	44.597us	19	20	95.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	1.040s	26.374us	20	20	100.00
	sram_ctrl_csr_aliasing	1.120s	24.876us	5	5	100.00
mem_walk				50	50	100.00
	sram_ctrl_mem_walk	14.080s	8232.636us	50	50	100.00
mem_partial_access				50	50	100.00
	sram_ctrl_mem_partial_access	7.030s	372.340us	50	50	100.00

890/890 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				50	50	100.00
	sram_ctrl_multiple_keys	1472.950s	302561.056us	50	50	100.00
stress_pipeline				50	50	100.00
	sram_ctrl_stress_pipeline	406.030s	45345.854us	50	50	100.00
bijection				50	50	100.00
	sram_ctrl_bijection	87.080s	18741.726us	50	50	100.00
access_during_key_req				50	50	100.00
	sram_ctrl_access_during_key_req	1285.940s	4508.740us	50	50	100.00
lc_escalation				50	50	100.00
	sram_ctrl_lc_escalation	14.760s	7730.741us	50	50	100.00
executable				50	50	100.00
	sram_ctrl_executable	1062.000s	3774.611us	50	50	100.00
partial_access				100	100	100.00
	sram_ctrl_partial_access	97.490s	223.720us	50	50	100.00
	sram_ctrl_partial_access_b2b	574.040s	110683.902us	50	50	100.00
max_throughput				150	150	100.00
	sram_ctrl_max_throughput	93.960s	528.981us	50	50	100.00
	sram_ctrl_throughput_w_partial_write	93.240s	155.720us	50	50	100.00
	sram_ctrl_throughput_w_readback	92.820s	284.867us	50	50	100.00
regwen				50	50	100.00
	sram_ctrl_regwen	1492.970s	90638.424us	50	50	100.00
ram_cfg				50	50	100.00
	sram_ctrl_ram_cfg	1.210s	39.294us	50	50	100.00
stress_all				50	50	100.00
	sram_ctrl_stress_all	3924.190s	13059.889us	50	50	100.00
alert_test				50	50	100.00
	sram_ctrl_alert_test	1.090s	26.826us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	5.490s	1016.027us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	5.490s	1016.027us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	1.050s	52.141us	5	5	100.00
	sram_ctrl_csr_rw	1.040s	26.374us	20	20	100.00
	sram_ctrl_csr_aliasing	1.120s	24.876us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.130s	35.136us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	1.050s	52.141us	5	5	100.00
	sram_ctrl_csr_rw	1.040s	26.374us	20	20	100.00
	sram_ctrl_csr_aliasing	1.120s	24.876us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.130s	35.136us	20	20	100.00

V2S

734/780 passed

94.10 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.380s	749.195us	20	20	100.00
tl_intg_err				20	25	80.00
	sram_ctrl_sec_cm	1.040s	13.269us	0	5	0.00
	sram_ctrl_tl_intg_err	3.210s	441.580us	20	20	100.00
prim_count_check				0	5	0.00
	sram_ctrl_sec_cm	1.040s	13.269us	0	5	0.00
sec_cm_bus_integrity				20	20	100.00
	sram_ctrl_tl_intg_err	3.210s	441.580us	20	20	100.00
sec_cm_ctrl_config_regwen				50	50	100.00
	sram_ctrl_regwen	1492.970s	90638.424us	50	50	100.00
sec_cm_readback_config_regwen				50	50	100.00
	sram_ctrl_regwen	1492.970s	90638.424us	50	50	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	1.040s	26.374us	20	20	100.00
sec_cm_exec_config_mubi				50	50	100.00
	sram_ctrl_executable	1062.000s	3774.611us	50	50	100.00
sec_cm_exec_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1062.000s	3774.611us	50	50	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1062.000s	3774.611us	50	50	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	sram_ctrl_lc_escalation	14.760s	7730.741us	50	50	100.00
sec_cm_prim_ram_ctrl_mubi				44	50	88.00
	sram_ctrl_mubi_enc_err	1.650s	102.701us	44	50	88.00
sec_cm_mem_integrity				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.380s	749.195us	20	20	100.00
sec_cm_mem_readback				40	50	80.00
	sram_ctrl_readback_err	1.480s	30.569us	40	50	80.00
sec_cm_mem_scramble				50	50	100.00
	sram_ctrl_smoke	100.280s	659.833us	50	50	100.00
sec_cm_addr_scramble				50	50	100.00
	sram_ctrl_smoke	100.280s	659.833us	50	50	100.00
sec_cm_instr_bus_lc_gated				50	50	100.00
	sram_ctrl_executable	1062.000s	3774.611us	50	50	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	5	0.00
	sram_ctrl_sec_cm	1.040s	13.269us	0	5	0.00
sec_cm_key_global_esc				50	50	100.00
	sram_ctrl_lc_escalation	14.760s	7730.741us	50	50	100.00
sec_cm_key_local_esc				0	5	0.00
	sram_ctrl_sec_cm	1.040s	13.269us	0	5	0.00
sec_cm_init_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.040s	13.269us	0	5	0.00
sec_cm_scramble_key_sideload				50	50	100.00
	sram_ctrl_smoke	100.280s	659.833us	50	50	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.040s	13.269us	0	5	0.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	sram_ctrl_stress_all_with_rand_reset	682.210s	4629.091us	50	50	100.00

Error Messages

	Test	seed	line	log context
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	sram_ctrl_sec_cm	15735704462387699900486506224809961234460245278000399352188414849026162947442	97	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1629946ps failed at 1629946ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1649946ps failed at 1649946ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	69176085729324824697028949933764655074560180375838391079546711693478888438334	97	UVM_ERROR @ 3592856 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 3592856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	102859388203932100838780683502879699003428929341984102953173758015413232329720	99	UVM_ERROR @ 13269372 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 13269372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	111588058471262890347192085446023270556870916139511065484650850117263399979138	96	UVM_ERROR @ 11282622 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 11282622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
	sram_ctrl_mubi_enc_err	78948682556418512522863933330883215516575805818549296961542737576044618940992	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 108927895 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 108927895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	26972616535228811168944374640952768312481713223908432441781526425550625224454	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 37367369 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 37367369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	31678144213184015531646575724357007722408217343272883823952107040087925758580	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 28134914 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 28134914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	107102226533213415182649356846280874198880661640222893228967712596665554676437	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 39523813 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 39523813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	71649247040053759497456713911868527040101684256694421058106290406059906975980	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 171094858 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 171094858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	31225127415270462655405542878754371585758227802129723259792887171600930721182	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 23709910 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 23709910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
	sram_ctrl_sec_cm	59598702528722601412344298064159094954566052532976352100849124697683363835887	98	Offending '(depth_o <= 2'(Depth))' UVM_ERROR @ 15761750 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth UVM_INFO @ 15761750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	50004876203294871971637183414074615232823709956824814857712221476676947765100	95	UVM_ERROR @ 194085287 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6c) != exp (0x32) UVM_INFO @ 194085287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	109110277109725199192585463674487433220339381529922592836077175017275587468783	95	UVM_ERROR @ 157515504 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x32) != exp (0x69) UVM_INFO @ 157515504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	113241026413676473570795832067552406796674818036490387496960816671092233787303	95	UVM_ERROR @ 28774993 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7b) != exp (0x74) UVM_INFO @ 28774993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	89718597283499266354071762063008150954099868923502399091315179177326714348486	95	UVM_ERROR @ 28153434 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2e) != exp (0x3d) UVM_INFO @ 28153434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	46147677703927108248824063444491623030064789491242967451392436562779001204290	95	UVM_ERROR @ 91107941 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4) != exp (0x3e) UVM_INFO @ 91107941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	53395124595977694484558736355623267600119841522290294291667528421708634504330	95	UVM_ERROR @ 22695426 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x39) UVM_INFO @ 22695426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	66858468031925762898182064919710236459905220696491530843265863521934319048456	95	UVM_ERROR @ 108581299 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x43) != exp (0x41) UVM_INFO @ 108581299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	88948099088110274726894138622329383103484077713939002064270799898481265656417	95	UVM_ERROR @ 90516774 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x26) != exp (0x6f) UVM_INFO @ 90516774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	84171848323767786853142233404209730863594103126297038841061909829917244936341	95	UVM_ERROR @ 45423202 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4) != exp (0x49) UVM_INFO @ 45423202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	97887866829087215126464609391363463599143666923705660224876514726540170112439	95	UVM_ERROR @ 27208357 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2c) != exp (0x49) UVM_INFO @ 27208357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	92603719764871050821091055532682776410440477102711946161269593577006890327444	101	UVM_ERROR @ 50967445 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: 0x0 UVM_INFO @ 50967445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---