ac_range_check Simulation Results

Simulation Results: ac_range_check

19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
83.28 %

code
93.54 %

assert
97.63 %

func
58.67 %

block
99.21 %

line
99.94 %

branch
98.35 %

toggle
82.34 %

Validation stages

V1		98.33%
V2		96.78%
V2S		100.00%
V3		100.00%
unmapped		100.00%

118/120 passed

98.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_smoke				19	20	95.00
	ac_range_check_smoke	77.000s	5046.779us	19	20	95.00
ac_range_check_smoke_racl				19	20	95.00
	ac_range_check_smoke_racl	85.000s	2948.326us	19	20	95.00
csr_hw_reset				5	5	100.00
	ac_range_check_csr_hw_reset	3.000s	43.632us	5	5	100.00
csr_rw				20	20	100.00
	ac_range_check_csr_rw	4.000s	108.937us	20	20	100.00
csr_bit_bash				5	5	100.00
	ac_range_check_csr_bit_bash	47.000s	2206.657us	5	5	100.00
csr_aliasing				5	5	100.00
	ac_range_check_csr_aliasing	28.000s	5607.936us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	ac_range_check_csr_mem_rw_with_rand_reset	3.000s	37.246us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	ac_range_check_csr_rw	4.000s	108.937us	20	20	100.00
	ac_range_check_csr_aliasing	28.000s	5607.936us	5	5	100.00

301/311 passed

96.78 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_lock_range				20	20	100.00
	ac_range_check_lock_range	4.000s	177.591us	20	20	100.00
ac_range_bypass_enable				1	1	100.00
	ac_range_check_bypass	54.000s	2288.476us	1	1	100.00
stress_all				40	50	80.00
	ac_range_check_stress_all	357.000s	11879.430us	40	50	80.00
alert_test				50	50	100.00
	ac_range_check_alert_test	3.000s	40.360us	50	50	100.00
intr_test				50	50	100.00
	ac_range_check_intr_test	2.000s	13.326us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	ac_range_check_tl_errors	7.000s	148.796us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	ac_range_check_tl_errors	7.000s	148.796us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	ac_range_check_csr_hw_reset	3.000s	43.632us	5	5	100.00
	ac_range_check_csr_rw	4.000s	108.937us	20	20	100.00
	ac_range_check_csr_aliasing	28.000s	5607.936us	5	5	100.00
	ac_range_check_same_csr_outstanding	8.000s	169.102us	20	20	100.00
tl_d_partial_access				50	50	100.00
	ac_range_check_csr_hw_reset	3.000s	43.632us	5	5	100.00
	ac_range_check_csr_rw	4.000s	108.937us	20	20	100.00
	ac_range_check_csr_aliasing	28.000s	5607.936us	5	5	100.00
	ac_range_check_same_csr_outstanding	8.000s	169.102us	20	20	100.00

V2S

125/125 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	ac_range_check_shadow_reg_errors	26.000s	12551.343us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	ac_range_check_shadow_reg_errors	26.000s	12551.343us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	ac_range_check_shadow_reg_errors	26.000s	12551.343us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	ac_range_check_shadow_reg_errors	26.000s	12551.343us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	ac_range_check_shadow_reg_errors_with_csr_rw	122.000s	9405.128us	20	20	100.00
tl_intg_err				25	25	100.00
	ac_range_check_sec_cm	2.000s	10.479us	5	5	100.00
	ac_range_check_tl_intg_err	17.000s	1680.760us	20	20	100.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	ac_range_check_stress_all_with_rand_reset	395.000s	5849.848us	50	50	100.00

unmapped

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				20	20	100.00
	ac_range_check_smoke_high_threshold	69.000s	4740.601us	20	20	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: ac_range_check_reg_block.intr_state
	ac_range_check_stress_all	81302208577428628266265018057811872944158179882808812910211208564587872298087	27507	UVM_ERROR @ 38020240459 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 38020240459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	40094882330238702946614719125131631836446202425391298162138395382618630081029	8807	UVM_ERROR @ 2077057645 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 2077057645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_smoke	23633756980628320196308175349997449091791673356550190637305524789940269461526	4109	UVM_ERROR @ 5120880119 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 5120880119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_smoke_racl	21752867806290072425479258165150391056011107996988898956247036938824444037783	4435	UVM_ERROR @ 9093875436 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 9093875436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	28794891419490493627871315096184359546940784912129207556336413728188268445406	8791	UVM_ERROR @ 3422691893 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 3422691893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	18806009758925654147202874215274801622563063921047033075290946005177973473254	13762	UVM_ERROR @ 1485862056 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 1485862056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	35432114554251322357696596255238875916071449065300417175714732171456208886127	4736	UVM_ERROR @ 1344513100 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 1344513100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	55392192220070186765973956206069549121130650348123145053476483490937924302317	12292	UVM_ERROR @ 5797127118 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 5797127118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	54693657916865365663062144632304842862745619836673975932429532859033508418123	4220	UVM_ERROR @ 3746666026 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 3746666026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_predictor.sv:163) [predict] Unable to get any item from tl_filt_d_chan_fifo.
	ac_range_check_stress_all	1894706617151399247531818780930708455202513814541775047257087738898163261602	21155	UVM_ERROR @ 100486875281 ps: (ac_range_check_predictor.sv:163) [uvm_test_top.env.scoreboard.predict] Unable to get any item from tl_filt_d_chan_fifo. UVM_INFO @ 100486875281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	77794166381981091875308240079434552717207003464283005176065291869128058975853	21001	UVM_ERROR @ 100354251374 ps: (ac_range_check_predictor.sv:163) [uvm_test_top.env.scoreboard.predict] Unable to get any item from tl_filt_d_chan_fifo. UVM_INFO @ 100354251374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_scoreboard.sv:166) [scoreboard] Unable to get any item from tl_unfilt_d_chan_fifo.
	ac_range_check_stress_all	69180774183076469660623026116613434387740544869372034089813541378389503155987	21597	UVM_ERROR @ 100302790563 ps: (ac_range_check_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Unable to get any item from tl_unfilt_d_chan_fifo. UVM_INFO @ 100302790563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---