| V1 |
|
98.47% |
| V2 |
|
99.85% |
| V2S |
|
95.44% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| aes_wake_up | 4.000s | 125.173us | 1 | 1 | 100.00 | |
| smoke | 50 | 50 | 100.00 | |||
| aes_smoke | 20.000s | 96.882us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| aes_csr_hw_reset | 6.000s | 97.418us | 5 | 5 | 100.00 | |
| csr_rw | 19 | 20 | 95.00 | |||
| aes_csr_rw | 6.000s | 76.358us | 19 | 20 | 95.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| aes_csr_bit_bash | 10.000s | 201.707us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| aes_csr_aliasing | 7.000s | 781.683us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| aes_csr_mem_rw_with_rand_reset | 3.000s | 57.308us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 24 | 25 | 96.00 | |||
| aes_csr_rw | 6.000s | 76.358us | 19 | 20 | 95.00 | |
| aes_csr_aliasing | 7.000s | 781.683us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| algorithm | 150 | 150 | 100.00 | |||
| aes_smoke | 20.000s | 96.882us | 50 | 50 | 100.00 | |
| aes_config_error | 21.000s | 541.006us | 50 | 50 | 100.00 | |
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| key_length | 150 | 150 | 100.00 | |||
| aes_smoke | 20.000s | 96.882us | 50 | 50 | 100.00 | |
| aes_config_error | 21.000s | 541.006us | 50 | 50 | 100.00 | |
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| back2back | 100 | 100 | 100.00 | |||
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| aes_b2b | 63.000s | 1373.727us | 50 | 50 | 100.00 | |
| backpressure | 50 | 50 | 100.00 | |||
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| multi_message | 200 | 200 | 100.00 | |||
| aes_smoke | 20.000s | 96.882us | 50 | 50 | 100.00 | |
| aes_config_error | 21.000s | 541.006us | 50 | 50 | 100.00 | |
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| aes_alert_reset | 22.000s | 589.267us | 50 | 50 | 100.00 | |
| failure_test | 150 | 150 | 100.00 | |||
| aes_man_cfg_err | 19.000s | 67.619us | 50 | 50 | 100.00 | |
| aes_config_error | 21.000s | 541.006us | 50 | 50 | 100.00 | |
| aes_alert_reset | 22.000s | 589.267us | 50 | 50 | 100.00 | |
| trigger_clear_test | 50 | 50 | 100.00 | |||
| aes_clear | 45.000s | 1979.629us | 50 | 50 | 100.00 | |
| nist_test_vectors | 1 | 1 | 100.00 | |||
| aes_nist_vectors | 9.000s | 191.062us | 1 | 1 | 100.00 | |
| reset_recovery | 50 | 50 | 100.00 | |||
| aes_alert_reset | 22.000s | 589.267us | 50 | 50 | 100.00 | |
| stress | 50 | 50 | 100.00 | |||
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| sideload | 100 | 100 | 100.00 | |||
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| aes_sideload | 20.000s | 94.094us | 50 | 50 | 100.00 | |
| deinitialization | 50 | 50 | 100.00 | |||
| aes_deinit | 22.000s | 1459.821us | 50 | 50 | 100.00 | |
| stress_all | 10 | 10 | 100.00 | |||
| aes_stress_all | 60.000s | 2070.352us | 10 | 10 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| aes_alert_test | 18.000s | 120.313us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| aes_tl_errors | 8.000s | 245.839us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| aes_tl_errors | 8.000s | 245.839us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 49 | 50 | 98.00 | |||
| aes_csr_hw_reset | 6.000s | 97.418us | 5 | 5 | 100.00 | |
| aes_csr_rw | 6.000s | 76.358us | 19 | 20 | 95.00 | |
| aes_csr_aliasing | 7.000s | 781.683us | 5 | 5 | 100.00 | |
| aes_same_csr_outstanding | 5.000s | 82.901us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 49 | 50 | 98.00 | |||
| aes_csr_hw_reset | 6.000s | 97.418us | 5 | 5 | 100.00 | |
| aes_csr_rw | 6.000s | 76.358us | 19 | 20 | 95.00 | |
| aes_csr_aliasing | 7.000s | 781.683us | 5 | 5 | 100.00 | |
| aes_same_csr_outstanding | 5.000s | 82.901us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reseeding | 50 | 50 | 100.00 | |||
| aes_reseed | 42.000s | 1888.086us | 50 | 50 | 100.00 | |
| fault_inject | 660 | 700 | 94.29 | |||
| aes_fi | 20.000s | 85.455us | 50 | 50 | 100.00 | |
| aes_control_fi | 57.000s | 10103.370us | 274 | 300 | 91.33 | |
| aes_cipher_fi | 59.000s | 10057.429us | 336 | 350 | 96.00 | |
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 7.000s | 139.593us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 7.000s | 139.593us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 7.000s | 139.593us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 7.000s | 139.593us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors_with_csr_rw | 7.000s | 220.180us | 20 | 20 | 100.00 | |
| tl_intg_err | 25 | 25 | 100.00 | |||
| aes_tl_intg_err | 7.000s | 489.271us | 20 | 20 | 100.00 | |
| aes_sec_cm | 21.000s | 440.105us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| aes_tl_intg_err | 7.000s | 489.271us | 20 | 20 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 50 | 50 | 100.00 | |||
| aes_alert_reset | 22.000s | 589.267us | 50 | 50 | 100.00 | |
| sec_cm_main_config_shadow | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 7.000s | 139.593us | 20 | 20 | 100.00 | |
| sec_cm_gcm_config_shadow | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 7.000s | 139.593us | 20 | 20 | 100.00 | |
| sec_cm_main_config_sparse | 218 | 220 | 99.09 | |||
| aes_smoke | 20.000s | 96.882us | 50 | 50 | 100.00 | |
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| aes_alert_reset | 22.000s | 589.267us | 50 | 50 | 100.00 | |
| aes_core_fi | 54.000s | 10080.423us | 68 | 70 | 97.14 | |
| sec_cm_gcm_config_sparse | 100 | 100 | 100.00 | |||
| aes_config_error | 21.000s | 541.006us | 50 | 50 | 100.00 | |
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| sec_cm_aux_config_shadow | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 7.000s | 139.593us | 20 | 20 | 100.00 | |
| sec_cm_aux_config_regwen | 100 | 100 | 100.00 | |||
| aes_readability | 17.000s | 72.487us | 50 | 50 | 100.00 | |
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| sec_cm_key_sideload | 100 | 100 | 100.00 | |||
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| aes_sideload | 20.000s | 94.094us | 50 | 50 | 100.00 | |
| sec_cm_key_sw_unreadable | 50 | 50 | 100.00 | |||
| aes_readability | 17.000s | 72.487us | 50 | 50 | 100.00 | |
| sec_cm_data_reg_sw_unreadable | 50 | 50 | 100.00 | |||
| aes_readability | 17.000s | 72.487us | 50 | 50 | 100.00 | |
| sec_cm_key_sec_wipe | 50 | 50 | 100.00 | |||
| aes_readability | 17.000s | 72.487us | 50 | 50 | 100.00 | |
| sec_cm_iv_config_sec_wipe | 50 | 50 | 100.00 | |||
| aes_readability | 17.000s | 72.487us | 50 | 50 | 100.00 | |
| sec_cm_data_reg_sec_wipe | 50 | 50 | 100.00 | |||
| aes_readability | 17.000s | 72.487us | 50 | 50 | 100.00 | |
| sec_cm_data_reg_key_sca | 50 | 50 | 100.00 | |||
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| sec_cm_key_masking | 50 | 50 | 100.00 | |||
| aes_stress | 19.000s | 170.658us | 50 | 50 | 100.00 | |
| sec_cm_main_fsm_sparse | 50 | 50 | 100.00 | |||
| aes_fi | 20.000s | 85.455us | 50 | 50 | 100.00 | |
| sec_cm_main_fsm_redun | 710 | 750 | 94.67 | |||
| aes_fi | 20.000s | 85.455us | 50 | 50 | 100.00 | |
| aes_control_fi | 57.000s | 10103.370us | 274 | 300 | 91.33 | |
| aes_cipher_fi | 59.000s | 10057.429us | 336 | 350 | 96.00 | |
| aes_ctr_fi | 19.000s | 78.642us | 50 | 50 | 100.00 | |
| sec_cm_cipher_fsm_sparse | 50 | 50 | 100.00 | |||
| aes_fi | 20.000s | 85.455us | 50 | 50 | 100.00 | |
| sec_cm_cipher_fsm_redun | 660 | 700 | 94.29 | |||
| aes_fi | 20.000s | 85.455us | 50 | 50 | 100.00 | |
| aes_control_fi | 57.000s | 10103.370us | 274 | 300 | 91.33 | |
| aes_cipher_fi | 59.000s | 10057.429us | 336 | 350 | 96.00 | |
| sec_cm_cipher_ctr_redun | 336 | 350 | 96.00 | |||
| aes_cipher_fi | 59.000s | 10057.429us | 336 | 350 | 96.00 | |
| sec_cm_ctr_fsm_sparse | 50 | 50 | 100.00 | |||
| aes_fi | 20.000s | 85.455us | 50 | 50 | 100.00 | |
| sec_cm_ctr_fsm_redun | 374 | 400 | 93.50 | |||
| aes_fi | 20.000s | 85.455us | 50 | 50 | 100.00 | |
| aes_control_fi | 57.000s | 10103.370us | 274 | 300 | 91.33 | |
| aes_ctr_fi | 19.000s | 78.642us | 50 | 50 | 100.00 | |
| sec_cm_ctrl_sparse | 710 | 750 | 94.67 | |||
| aes_fi | 20.000s | 85.455us | 50 | 50 | 100.00 | |
| aes_control_fi | 57.000s | 10103.370us | 274 | 300 | 91.33 | |
| aes_cipher_fi | 59.000s | 10057.429us | 336 | 350 | 96.00 | |
| aes_ctr_fi | 19.000s | 78.642us | 50 | 50 | 100.00 | |
| sec_cm_main_fsm_global_esc | 50 | 50 | 100.00 | |||
| aes_alert_reset | 22.000s | 589.267us | 50 | 50 | 100.00 | |
| sec_cm_main_fsm_local_esc | 710 | 750 | 94.67 | |||
| aes_fi | 20.000s | 85.455us | 50 | 50 | 100.00 | |
| aes_control_fi | 57.000s | 10103.370us | 274 | 300 | 91.33 | |
| aes_cipher_fi | 59.000s | 10057.429us | 336 | 350 | 96.00 | |
| aes_ctr_fi | 19.000s | 78.642us | 50 | 50 | 100.00 | |
| sec_cm_cipher_fsm_local_esc | 710 | 750 | 94.67 | |||
| aes_fi | 20.000s | 85.455us | 50 | 50 | 100.00 | |
| aes_control_fi | 57.000s | 10103.370us | 274 | 300 | 91.33 | |
| aes_cipher_fi | 59.000s | 10057.429us | 336 | 350 | 96.00 | |
| aes_ctr_fi | 19.000s | 78.642us | 50 | 50 | 100.00 | |
| sec_cm_ctr_fsm_local_esc | 374 | 400 | 93.50 | |||
| aes_fi | 20.000s | 85.455us | 50 | 50 | 100.00 | |
| aes_control_fi | 57.000s | 10103.370us | 274 | 300 | 91.33 | |
| aes_ctr_fi | 19.000s | 78.642us | 50 | 50 | 100.00 | |
| sec_cm_data_reg_local_esc | 660 | 700 | 94.29 | |||
| aes_fi | 20.000s | 85.455us | 50 | 50 | 100.00 | |
| aes_control_fi | 57.000s | 10103.370us | 274 | 300 | 91.33 | |
| aes_cipher_fi | 59.000s | 10057.429us | 336 | 350 | 96.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| aes_stress_all_with_rand_reset | 30.000s | 1084.212us | 0 | 10 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,876): Assertion AesSecCmKeyMaskingStateShare has failed (* cycles, starting * PS) | ||||
| aes_csr_rw | 26605043389264252710670479539081440277186634840128423231874352919318755831159 | 106 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,876): (time 3285149 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.gen_sec_cm_key_masking_share_svas[1].AesSecCmKeyMaskingStateShare has failed (2 cycles, starting 3274732 PS)
UVM_ERROR @ 3285149 ps: (aes_cipher_core.sv:876) [ASSERT FAILED] AesSecCmKeyMaskingStateShare
UVM_INFO @ 3285149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| aes_stress_all_with_rand_reset | 30041315623123174587625128506655193176904346264083492116905226616770619241427 | 650 |
UVM_ERROR @ 1361159022 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1361159022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 16126939491151206295539337417669508196306041858858264931162239439175512903853 | 365 |
UVM_ERROR @ 1089281691 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1089281691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 43940108776998228148883472328470537628477542900104614477110903985966444780490 | 306 |
UVM_ERROR @ 166400942 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 166400942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) | ||||
| aes_stress_all_with_rand_reset | 48109911797864994081697177482174372381228687575559290014336037346715302921779 | 149 |
UVM_FATAL @ 83018926 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 83018926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 33881057885600311609801037452391502170198643432916824473638760730245173406452 | 302 |
UVM_FATAL @ 513405759 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 513405759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 78905186269028791373288409053809571794800582675478101689260733905796068397053 | 152 |
UVM_FATAL @ 83497900 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 83497900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! | ||||
| aes_core_fi | 63255865188041646946131025328112250421445862413191026853377887148117941798386 | 143 |
UVM_FATAL @ 10011547416 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10011547416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 83421257491089242726028997407008348366924379819491500644514092057035866288399 | 134 |
UVM_FATAL @ 10080423339 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10080423339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) | ||||
| aes_stress_all_with_rand_reset | 75342413566165655600414567336207721622061050772745364650200195784824573904488 | 617 |
UVM_FATAL @ 1084211953 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 1084211953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! | ||||
| aes_cipher_fi | 81299051390302361670721169014910621972018983326372227417155304517770223909310 | 137 |
UVM_FATAL @ 10021153656 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10021153656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 9451252034014219075566208419645013916105741827817818265566338246789877760919 | 143 |
UVM_FATAL @ 10017335818 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10017335818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 71369372130929599803084366719291440737368693764111403330533894037323875121202 | 135 |
UVM_FATAL @ 10014266333 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10014266333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 41583306972538237963360147300433341558615752736728619675112668494888098408095 | 140 |
UVM_FATAL @ 10006499886 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006499886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 31766405542249545202173259971739866600634830623982987600068976164711456694660 | 139 |
UVM_FATAL @ 10014232975 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10014232975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 77278235691647411208193456041607633377371773972413652740331323601787904626675 | 132 |
UVM_FATAL @ 10007630669 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007630669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 110875848383528341961251890605439095733954675587172882233181681739354286845061 | 137 |
UVM_FATAL @ 10057428930 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10057428930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| aes_stress_all_with_rand_reset | 104968106517367872432998944471311243385133516041832784919372949603824313474648 | 258 |
UVM_ERROR @ 226090922 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 226090922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 110280604420988117080536693936759801695505207795241036191751716562767308363407 | 159 |
UVM_ERROR @ 2880587573 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2880587573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 93226421807660865432271760962130036731959396553459990884133083534583189317579 | 153 |
UVM_ERROR @ 257444736 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 257444736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | ||||
| aes_control_fi | 82566781506058645346670615349800662297650722847537290999084893932813323148979 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 112076325323304700694822509481541647699333727041928949026124163786563087378389 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 6427653257837039000696764365630516444932135385989196830952543672405311826513 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 42852607060008568208598742324241550952075029100973322895540380681001333588962 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 62864523836029574732036909477957580473900453388639788964681867244479253912926 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 14689605303438985536646528654070413611333520058919309240928309285090570411375 | None |
Job timed out after 1 minutes
|
|
| aes_cipher_fi | 28971000334413145367655770666665642346504124645955712231287313239103454815727 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 14882094493914988014794324744476508239091562314238066861124245229635315884436 | None |
Job timed out after 1 minutes
|
|
| aes_cipher_fi | 50404480051184536838420943519650213602901573689317331406201103555547022039733 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 42279307983500961431657098708156404397605389617554228140685165212845882796 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 64894759376854323284546840316021715483316719184506038130297709849141162731969 | None |
Job timed out after 1 minutes
|
|
| aes_cipher_fi | 88491047104586112383608515433511399761708477704816872704476752283966564215660 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 10785263348183798118266988719185224935075306056864164490768713508198536415155 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 51315767812738906303888328836510599081075321245608503143455087764820180569277 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 44743998206875728035951049622910663588536234736696573389151226680540458949866 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 97716907272117024971233204827418136214621268714647135348081388166351537573498 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 95565452032699125675087738158830874389278861296352846486520301597855815268138 | None |
Job timed out after 1 minutes
|
|
| aes_cipher_fi | 75756968445232425678912352048507794038921239701784376960539375179013589881818 | None |
Job timed out after 1 minutes
|
|
| aes_cipher_fi | 21738592988791290999788725037267098066898873844199373875598660817499803932575 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 39765840436656412201642498014039801157350796068793496071898687127218657830636 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 66746272381683246792418436106975111192113832795954289626053691935684104678582 | None |
Job timed out after 1 minutes
|
|
| aes_cipher_fi | 59835145257741703454651049541915498427200102203577482148625780645375015262810 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 77101509853486839085829543731033733948074640211585065754156735387352098064378 | None |
Job timed out after 1 minutes
|
|
| aes_cipher_fi | 103357582051077099229361125840141348275276870395315688437251217489081491464939 | None |
Job timed out after 1 minutes
|
|
| UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! | ||||
| aes_control_fi | 96423718538912056889307521828201379293281771667326707544614581631244211713719 | 136 |
UVM_FATAL @ 10027783615 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10027783615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 63472859201640977875626338200883872925988164064503341376237294011224402294479 | 138 |
UVM_FATAL @ 10023067993 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10023067993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 97728596307875847383729262669470575062965927674132860960431774670870236272236 | 146 |
UVM_FATAL @ 10015153301 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10015153301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 101537510574095205615771921635079442052989196840574839027389383540848411996524 | 146 |
UVM_FATAL @ 10010974699 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10010974699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 88695882923762655806120875225928208445538026158948711089565130670996187111074 | 145 |
UVM_FATAL @ 10103369942 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10103369942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 41610700467231998655092425602781725017677006750083401194415435509174775024878 | 136 |
UVM_FATAL @ 10011624446 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10011624446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 31761072108116280988122818690948887679505096929768460136046246375958750823798 | 141 |
UVM_FATAL @ 10007337220 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007337220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 71371882206128532047156698541253605827746723176017359772155551621505318231505 | 132 |
UVM_FATAL @ 10020682635 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10020682635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 32373109638869132696637219995101590826909996924735876300342176562401481667085 | 145 |
UVM_FATAL @ 10008766785 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10008766785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|