Simulation Results: dma

 
19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.10 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 79.13 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 7.000s 576.394us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 10.000s 1768.965us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 8.000s 1197.055us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 102.171us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 37.257us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 13.000s 5913.559us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 7.000s 554.639us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 3.000s 53.814us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 37.257us 20 20 100.00
dma_csr_aliasing 7.000s 554.639us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 88.000s 12531.056us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 730.000s 807890.521us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 1301.000s 120212.490us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 1301.000s 120212.490us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 730.000s 807890.521us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 980.000s 319479.357us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 1301.000s 120212.490us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 13.000s 4609.023us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 219.000s 75702.393us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 16.135us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 27.840us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 3.000s 162.178us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 3.000s 162.178us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 102.171us 5 5 100.00
dma_csr_rw 2.000s 37.257us 20 20 100.00
dma_csr_aliasing 7.000s 554.639us 5 5 100.00
dma_same_csr_outstanding 3.000s 364.831us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 102.171us 5 5 100.00
dma_csr_rw 2.000s 37.257us 20 20 100.00
dma_csr_aliasing 7.000s 554.639us 5 5 100.00
dma_same_csr_outstanding 3.000s 364.831us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 23.000s 340.252us 5 5 100.00
dma_generic_stress 980.000s 319479.357us 5 5 100.00
dma_handshake_stress 1301.000s 120212.490us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 11.000s 328.403us 15 15 100.00
tl_intg_err 25 25 100.00
dma_sec_cm 2.000s 13.848us 5 5 100.00
dma_tl_intg_err 4.000s 181.303us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 154.000s 13119.294us 25 25 100.00
dma_longer_transfer 12.000s 626.464us 5 5 100.00
dma_stress_all_with_rand_reset 4.000s 110.673us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 108500303127169674204833120227966561586107102897936279845178579371244983054889 92
UVM_ERROR @ 110673052ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 110673052ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---