Simulation Results: edn

 
19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.50 %
  • code
  • 95.83 %
  • assert
  • 97.61 %
  • func
  • 93.06 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.14 %
  • toggle
  • 97.12 %
  • FSM
  • 92.47 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.070s 73.849us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.840s 57.568us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.930s 32.719us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.560s 706.687us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.050s 65.782us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.310s 126.934us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.930s 32.719us 20 20 100.00
edn_csr_aliasing 1.050s 65.782us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 118.600s 12948.967us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 118.600s 12948.967us 300 300 100.00
genbits 300 300 100.00
edn_genbits 118.600s 12948.967us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.070s 21.524us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.480s 48.676us 200 200 100.00
errs 100 100 100.00
edn_err 1.680s 28.839us 100 100 100.00
disable 100 100 100.00
edn_disable 1.030s 22.076us 50 50 100.00
edn_disable_auto_req_mode 1.320s 33.437us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 4.950s 367.173us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.860s 55.420us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.270s 30.203us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.270s 608.649us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.270s 608.649us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.840s 57.568us 5 5 100.00
edn_csr_rw 0.930s 32.719us 20 20 100.00
edn_csr_aliasing 1.050s 65.782us 5 5 100.00
edn_same_csr_outstanding 1.230s 115.714us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.840s 57.568us 5 5 100.00
edn_csr_rw 0.930s 32.719us 20 20 100.00
edn_csr_aliasing 1.050s 65.782us 5 5 100.00
edn_same_csr_outstanding 1.230s 115.714us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 2.330s 658.193us 20 20 100.00
edn_sec_cm 4.030s 1335.770us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.900s 16.662us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.480s 48.676us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.030s 1335.770us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.030s 1335.770us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.030s 1335.770us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.030s 1335.770us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.480s 48.676us 200 200 100.00
edn_sec_cm 4.030s 1335.770us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.480s 48.676us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.330s 658.193us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 49 50 98.00
edn_stress_all_with_rand_reset 89.520s 10220.786us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1142) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
edn_stress_all_with_rand_reset 57547715837339334062270012222918477123539560465227162673692406905213589833283 145
UVM_ERROR @ 371878738 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 371878738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---