Simulation Results: edn

 
19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.25 %
  • code
  • 96.39 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.210s 20.378us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.840s 69.686us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.770s 31.229us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.930s 255.359us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.080s 123.248us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.300s 27.939us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.770s 31.229us 20 20 100.00
edn_csr_aliasing 1.080s 123.248us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 5.270s 856.910us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 5.270s 856.910us 300 300 100.00
genbits 300 300 100.00
edn_genbits 5.270s 856.910us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.190s 21.219us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.410s 96.512us 200 200 100.00
errs 100 100 100.00
edn_err 1.410s 176.047us 100 100 100.00
disable 100 100 100.00
edn_disable 1.130s 30.203us 50 50 100.00
edn_disable_auto_req_mode 1.480s 52.640us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 4.230s 700.951us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.850s 42.846us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.140s 35.047us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.460s 191.781us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.460s 191.781us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.840s 69.686us 5 5 100.00
edn_csr_rw 0.770s 31.229us 20 20 100.00
edn_csr_aliasing 1.080s 123.248us 5 5 100.00
edn_same_csr_outstanding 1.140s 60.326us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.840s 69.686us 5 5 100.00
edn_csr_rw 0.770s 31.229us 20 20 100.00
edn_csr_aliasing 1.080s 123.248us 5 5 100.00
edn_same_csr_outstanding 1.140s 60.326us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 2.120s 147.429us 20 20 100.00
edn_sec_cm 3.610s 393.068us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.790s 15.154us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.410s 96.512us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.610s 393.068us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.610s 393.068us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 3.610s 393.068us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 3.610s 393.068us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.410s 96.512us 200 200 100.00
edn_sec_cm 3.610s 393.068us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.410s 96.512us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.120s 147.429us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 82.150s 19982.610us 50 50 100.00

Error Messages

   Test seed line log context